445959821f
This patch changes 24xx to use new register access, except for clock framework. Clock framework register access will get updates in the next patch. Note that board-*.c files change GPMC (General Purpose Memory Controller) access to use gpmc_cs_write_reg() instead of accessing the registers directly. The code also uses gpmc_fck instead of it's parent clock core_l3_ck for GPMC clock. The H4 board file also adds h4_init_flash() function, which specify the flash start and end addresses. Also note that sleep.S removes some unused registers addresses. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
124 lines
3.0 KiB
C
124 lines
3.0 KiB
C
/*
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* linux/arch/arm/mach-omap2/memory.c
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*
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* Memory timing related functions for OMAP24XX
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*
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* Copyright (C) 2005 Texas Instruments Inc.
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* Richard Woodruff <r-woodruff2@ti.com>
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*
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* Copyright (C) 2005 Nokia Corporation
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* Tony Lindgren <tony@atomide.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sram.h>
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#include "prm.h"
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#include "memory.h"
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#include "sdrc.h"
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unsigned long omap2_sdrc_base;
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unsigned long omap2_sms_base;
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static struct memory_timings mem_timings;
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static u32 curr_perf_level = CORE_CLK_SRC_DPLL_X2;
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u32 omap2_memory_get_slow_dll_ctrl(void)
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{
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return mem_timings.slow_dll_ctrl;
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}
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u32 omap2_memory_get_fast_dll_ctrl(void)
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{
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return mem_timings.fast_dll_ctrl;
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}
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u32 omap2_memory_get_type(void)
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{
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return mem_timings.m_type;
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}
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void omap2_init_memory_params(u32 force_lock_to_unlock_mode)
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{
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unsigned long dll_cnt;
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u32 fast_dll = 0;
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mem_timings.m_type = !((sdrc_read_reg(SDRC_MR_0) & 0x3) == 0x1); /* DDR = 1, SDR = 0 */
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/* 2422 es2.05 and beyond has a single SIP DDR instead of 2 like others.
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* In the case of 2422, its ok to use CS1 instead of CS0.
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*/
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if (cpu_is_omap2422())
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mem_timings.base_cs = 1;
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else
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mem_timings.base_cs = 0;
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if (mem_timings.m_type != M_DDR)
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return;
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/* With DDR we need to determine the low frequency DLL value */
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if (((mem_timings.fast_dll_ctrl & (1 << 2)) == M_LOCK_CTRL))
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mem_timings.dll_mode = M_UNLOCK;
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else
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mem_timings.dll_mode = M_LOCK;
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if (mem_timings.base_cs == 0) {
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fast_dll = sdrc_read_reg(SDRC_DLLA_CTRL);
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dll_cnt = sdrc_read_reg(SDRC_DLLA_STATUS) & 0xff00;
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} else {
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fast_dll = sdrc_read_reg(SDRC_DLLB_CTRL);
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dll_cnt = sdrc_read_reg(SDRC_DLLB_STATUS) & 0xff00;
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}
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if (force_lock_to_unlock_mode) {
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fast_dll &= ~0xff00;
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fast_dll |= dll_cnt; /* Current lock mode */
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}
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/* set fast timings with DLL filter disabled */
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mem_timings.fast_dll_ctrl = (fast_dll | (3 << 8));
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/* No disruptions, DDR will be offline & C-ABI not followed */
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omap2_sram_ddr_init(&mem_timings.slow_dll_ctrl,
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mem_timings.fast_dll_ctrl,
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mem_timings.base_cs,
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force_lock_to_unlock_mode);
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mem_timings.slow_dll_ctrl &= 0xff00; /* Keep lock value */
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/* Turn status into unlock ctrl */
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mem_timings.slow_dll_ctrl |=
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((mem_timings.fast_dll_ctrl & 0xF) | (1 << 2));
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/* 90 degree phase for anything below 133Mhz + disable DLL filter */
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mem_timings.slow_dll_ctrl |= ((1 << 1) | (3 << 8));
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}
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/* turn on smart idle modes for SDRAM scheduler and controller */
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void __init omap2_init_memory(void)
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{
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u32 l;
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l = sms_read_reg(SMS_SYSCONFIG);
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l &= ~(0x3 << 3);
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l |= (0x2 << 3);
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sms_write_reg(l, SMS_SYSCONFIG);
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l = sdrc_read_reg(SDRC_SYSCONFIG);
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l &= ~(0x3 << 3);
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l |= (0x2 << 3);
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sdrc_write_reg(l, SDRC_SYSCONFIG);
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}
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