efdf72ad5c
The frequency memory bus on Tegra can be adjusted without disabling accesses to memory by updating the memory configuration registers from a per-board table, and then changing the clock frequency. The clock controller and memory controller have an interlock that prevents the new memory registers from taking effect until the clock frequency change. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
28 lines
831 B
C
28 lines
831 B
C
/*
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* Copyright (C) 2011 Google, Inc.
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*
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* Author:
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* Colin Cross <ccross@android.com>
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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*/
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#define TEGRA_EMC_NUM_REGS 46
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struct tegra_emc_table {
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unsigned long rate;
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u32 regs[TEGRA_EMC_NUM_REGS];
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};
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int tegra_emc_set_rate(unsigned long rate);
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long tegra_emc_round_rate(unsigned long rate);
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void tegra_init_emc(const struct tegra_emc_table *table, int table_size);
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