428aac8a81
All 4 transfer types can work well on EHCI HCD after switching to run URB giveback in tasklet context, so mark all HCD drivers to support it. Also we don't need to release ehci->lock during URB giveback any more. >From below test results on 3 machines(2 ARM and one x86), time consumed by EHCI interrupt handler droped much without performance loss. 1 test description 1.1 mass storage performance test: - run below command 10 times and compute the average performance dd if=/dev/sdN iflag=direct of=/dev/null bs=200M count=1 - two usb mass storage device: A: sandisk extreme USB 3.0 16G(used in test case 1 & case 2) B: kingston DataTraveler G2 4GB(only used in test case 2) 1.2 uvc function test: - run one simple capture program in the below link http://kernel.ubuntu.com/~ming/up/capture.c - capture format 640*480 and results in High Bandwidth mode on the uvc device: Z-Star 0x0ac8/0x3450 - on T410(x86) laptop, also use guvcview to watch video capture/playback 1.3 about test2 and test4 - both two devices involved are tested concurrently by above test items 1.4 how to compute irq time(the time consumed by ehci_irq) - use trace points of irq:irq_handler_entry and irq:irq_handler_exit 1.5 kernel 3.10.0-rc3-next-20130528 1.6 test machines Pandaboard A1: ARM CortexA9 dural core Arndale board: ARM CortexA15 dural core T410: i5 CPU 2.67GHz quad core 2 test result 2.1 test case1: single mass storage device performance test -------------------------------------------------------------------- upstream | patched perf(MB/s)+irq time(us) | perf(MB/s)+irq time(us) -------------------------------------------------------------------- Pandaboard A1: 25.280(avg:145,max:772) | 25.540(avg:14, max:75) Arndale board: 29.700(avg:33, max:129) | 29.700(avg:10, max:50) T410: 34.430(avg:17, max:154*)| 34.660(avg:12, max:155) --------------------------------------------------------------------- 2.2 test case2: two mass storage devices' performance test -------------------------------------------------------------------- upstream | patched perf(MB/s)+irq time(us) | perf(MB/s)+irq time(us) -------------------------------------------------------------------- Pandaboard A1: 15.840/15.580(avg:158,max:1216) | 16.500/16.160(avg:15,max:139) Arndale board: 17.370/16.220(avg:33 max:234) | 17.480/16.200(avg:11, max:91) T410: 21.180/19.820(avg:18 max:160) | 21.220/19.880(avg:11, max:149) --------------------------------------------------------------------- 2.3 test case3: one uvc streaming test - uvc device works well(on x86, luvcview can be used too and has same result with uvc capture) -------------------------------------------------------------------- upstream | patched irq time(us) | irq time(us) -------------------------------------------------------------------- Pandaboard A1: (avg:445, max:873) | (avg:33, max:44) Arndale board: (avg:316, max:630) | (avg:20, max:27) T410: (avg:39, max:107) | (avg:10, max:65) --------------------------------------------------------------------- 2.4 test case4: one uvc streaming plus one mass storage device test -------------------------------------------------------------------- upstream | patched perf(MB/s)+irq time(us) | perf(MB/s)+irq time(us) -------------------------------------------------------------------- Pandaboard A1: 20.340(avg:259,max:1704)| 20.390(avg:24, max:101) Arndale board: 23.460(avg:124,max:726) | 23.370(avg:15, max:52) T410: 28.520(avg:27, max:169) | 28.630(avg:13, max:160) --------------------------------------------------------------------- 2.5 test case5: read single mass storage device with small transfer - run below command 10 times and compute the average speed dd if=/dev/sdN iflag=direct of=/dev/null bs=4K count=4000 1), test device A: -------------------------------------------------------------------- upstream | patched perf(MB/s)+irq time(us) | perf(MB/s)+irq time(us) -------------------------------------------------------------------- Pandaboard A1: 6.5(avg:21, max:64) | 6.5(avg:10, max:24) Arndale board: 8.13(avg:12, max:23) | 8.06(avg:7, max:17) T410: 6.66(avg:13, max:131) | 6.84(avg:11, max:149) --------------------------------------------------------------------- 2), test device B: -------------------------------------------------------------------- upstream | patched perf(MB/s)+irq time(us) | perf(MB/s)+irq time(us) -------------------------------------------------------------------- Pandaboard A1: 5.5(avg:21,max:43) | 5.49(avg:10, max:24) Arndale board: 5.9(avg:12, max:22) | 5.9(avg:7, max:17) T410: 5.48(avg:13, max:155) | 5.48(avg:7, max:140) --------------------------------------------------------------------- * On T410, sometimes read ehci status register in ehci_irq takes more than 100us, and the problem has been reported on the link: http://marc.info/?t=137065867300001&r=1&w=2 Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Ming Lei <ming.lei@canonical.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
266 lines
6.8 KiB
C
266 lines
6.8 KiB
C
/*
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* PS3 EHCI Host Controller driver
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*
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* Copyright (C) 2006 Sony Computer Entertainment Inc.
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* Copyright 2006 Sony Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <asm/firmware.h>
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#include <asm/ps3.h>
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static void ps3_ehci_setup_insnreg(struct ehci_hcd *ehci)
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{
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/* PS3 HC internal setup register offsets. */
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enum ps3_ehci_hc_insnreg {
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ps3_ehci_hc_insnreg01 = 0x084,
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ps3_ehci_hc_insnreg02 = 0x088,
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ps3_ehci_hc_insnreg03 = 0x08c,
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};
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/* PS3 EHCI HC errata fix 316 - The PS3 EHCI HC will reset its
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* internal INSNREGXX setup regs back to the chip default values
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* on Host Controller Reset (CMD_RESET) or Light Host Controller
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* Reset (CMD_LRESET). The work-around for this is for the HC
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* driver to re-initialise these regs when ever the HC is reset.
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*/
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/* Set burst transfer counts to 256 out, 32 in. */
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writel_be(0x01000020, (void __iomem *)ehci->regs +
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ps3_ehci_hc_insnreg01);
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/* Enable burst transfer counts. */
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writel_be(0x00000001, (void __iomem *)ehci->regs +
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ps3_ehci_hc_insnreg03);
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}
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static int ps3_ehci_hc_reset(struct usb_hcd *hcd)
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{
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int result;
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struct ehci_hcd *ehci = hcd_to_ehci(hcd);
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ehci->big_endian_mmio = 1;
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ehci->caps = hcd->regs;
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result = ehci_setup(hcd);
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if (result)
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return result;
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ps3_ehci_setup_insnreg(ehci);
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return result;
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}
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static const struct hc_driver ps3_ehci_hc_driver = {
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.description = hcd_name,
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.product_desc = "PS3 EHCI Host Controller",
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.hcd_priv_size = sizeof(struct ehci_hcd),
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.irq = ehci_irq,
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.flags = HCD_MEMORY | HCD_USB2 | HCD_BH,
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.reset = ps3_ehci_hc_reset,
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.start = ehci_run,
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.stop = ehci_stop,
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.shutdown = ehci_shutdown,
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.urb_enqueue = ehci_urb_enqueue,
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.urb_dequeue = ehci_urb_dequeue,
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.endpoint_disable = ehci_endpoint_disable,
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.endpoint_reset = ehci_endpoint_reset,
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.get_frame_number = ehci_get_frame,
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.hub_status_data = ehci_hub_status_data,
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.hub_control = ehci_hub_control,
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#if defined(CONFIG_PM)
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.bus_suspend = ehci_bus_suspend,
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.bus_resume = ehci_bus_resume,
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#endif
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.relinquish_port = ehci_relinquish_port,
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.port_handed_over = ehci_port_handed_over,
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.clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
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};
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static int ps3_ehci_probe(struct ps3_system_bus_device *dev)
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{
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int result;
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struct usb_hcd *hcd;
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unsigned int virq;
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static u64 dummy_mask = DMA_BIT_MASK(32);
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if (usb_disabled()) {
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result = -ENODEV;
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goto fail_start;
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}
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result = ps3_open_hv_device(dev);
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if (result) {
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dev_dbg(&dev->core, "%s:%d: ps3_open_hv_device failed\n",
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__func__, __LINE__);
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goto fail_open;
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}
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result = ps3_dma_region_create(dev->d_region);
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if (result) {
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dev_dbg(&dev->core, "%s:%d: ps3_dma_region_create failed: "
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"(%d)\n", __func__, __LINE__, result);
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BUG_ON("check region type");
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goto fail_dma_region;
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}
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result = ps3_mmio_region_create(dev->m_region);
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if (result) {
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dev_dbg(&dev->core, "%s:%d: ps3_map_mmio_region failed\n",
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__func__, __LINE__);
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result = -EPERM;
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goto fail_mmio_region;
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}
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dev_dbg(&dev->core, "%s:%d: mmio mapped_addr %lxh\n", __func__,
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__LINE__, dev->m_region->lpar_addr);
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result = ps3_io_irq_setup(PS3_BINDING_CPU_ANY, dev->interrupt_id, &virq);
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if (result) {
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dev_dbg(&dev->core, "%s:%d: ps3_construct_io_irq(%d) failed.\n",
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__func__, __LINE__, virq);
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result = -EPERM;
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goto fail_irq;
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}
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dev->core.dma_mask = &dummy_mask; /* FIXME: for improper usb code */
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hcd = usb_create_hcd(&ps3_ehci_hc_driver, &dev->core, dev_name(&dev->core));
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if (!hcd) {
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dev_dbg(&dev->core, "%s:%d: usb_create_hcd failed\n", __func__,
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__LINE__);
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result = -ENOMEM;
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goto fail_create_hcd;
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}
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hcd->rsrc_start = dev->m_region->lpar_addr;
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hcd->rsrc_len = dev->m_region->len;
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if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name))
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dev_dbg(&dev->core, "%s:%d: request_mem_region failed\n",
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__func__, __LINE__);
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hcd->regs = ioremap(dev->m_region->lpar_addr, dev->m_region->len);
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if (!hcd->regs) {
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dev_dbg(&dev->core, "%s:%d: ioremap failed\n", __func__,
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__LINE__);
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result = -EPERM;
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goto fail_ioremap;
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}
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dev_dbg(&dev->core, "%s:%d: hcd->rsrc_start %lxh\n", __func__, __LINE__,
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(unsigned long)hcd->rsrc_start);
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dev_dbg(&dev->core, "%s:%d: hcd->rsrc_len %lxh\n", __func__, __LINE__,
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(unsigned long)hcd->rsrc_len);
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dev_dbg(&dev->core, "%s:%d: hcd->regs %lxh\n", __func__, __LINE__,
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(unsigned long)hcd->regs);
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dev_dbg(&dev->core, "%s:%d: virq %lu\n", __func__, __LINE__,
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(unsigned long)virq);
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ps3_system_bus_set_drvdata(dev, hcd);
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result = usb_add_hcd(hcd, virq, 0);
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if (result) {
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dev_dbg(&dev->core, "%s:%d: usb_add_hcd failed (%d)\n",
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__func__, __LINE__, result);
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goto fail_add_hcd;
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}
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return result;
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fail_add_hcd:
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iounmap(hcd->regs);
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fail_ioremap:
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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usb_put_hcd(hcd);
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fail_create_hcd:
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ps3_io_irq_destroy(virq);
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fail_irq:
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ps3_free_mmio_region(dev->m_region);
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fail_mmio_region:
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ps3_dma_region_free(dev->d_region);
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fail_dma_region:
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ps3_close_hv_device(dev);
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fail_open:
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fail_start:
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return result;
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}
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static int ps3_ehci_remove(struct ps3_system_bus_device *dev)
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{
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unsigned int tmp;
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struct usb_hcd *hcd = ps3_system_bus_get_drvdata(dev);
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BUG_ON(!hcd);
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dev_dbg(&dev->core, "%s:%d: regs %p\n", __func__, __LINE__, hcd->regs);
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dev_dbg(&dev->core, "%s:%d: irq %u\n", __func__, __LINE__, hcd->irq);
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tmp = hcd->irq;
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usb_remove_hcd(hcd);
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ps3_system_bus_set_drvdata(dev, NULL);
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BUG_ON(!hcd->regs);
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iounmap(hcd->regs);
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release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
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usb_put_hcd(hcd);
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ps3_io_irq_destroy(tmp);
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ps3_free_mmio_region(dev->m_region);
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ps3_dma_region_free(dev->d_region);
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ps3_close_hv_device(dev);
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return 0;
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}
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static int __init ps3_ehci_driver_register(struct ps3_system_bus_driver *drv)
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{
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return firmware_has_feature(FW_FEATURE_PS3_LV1)
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? ps3_system_bus_driver_register(drv)
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: 0;
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}
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static void ps3_ehci_driver_unregister(struct ps3_system_bus_driver *drv)
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{
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if (firmware_has_feature(FW_FEATURE_PS3_LV1))
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ps3_system_bus_driver_unregister(drv);
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}
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MODULE_ALIAS(PS3_MODULE_ALIAS_EHCI);
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static struct ps3_system_bus_driver ps3_ehci_driver = {
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.core.name = "ps3-ehci-driver",
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.core.owner = THIS_MODULE,
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.match_id = PS3_MATCH_ID_EHCI,
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.probe = ps3_ehci_probe,
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.remove = ps3_ehci_remove,
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.shutdown = ps3_ehci_remove,
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};
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