b3b0b4580b
McPDM is the interface between Phoenix audio codec and the OMAP4430 processor. It enables data to be transfered to/from Phoenix at sample rates of 88.4 or 96 KHz. Signed-off-by: Jorge Eduardo Candelaria <jorge.candelaria@ti.com> Signed-off-by: Margarita Olaya <x0080101@ti.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
152 lines
4.3 KiB
C
152 lines
4.3 KiB
C
/*
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* mcpdm.h -- Defines for McPDM driver
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*
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* Author: Jorge Eduardo Candelaria <x0107209@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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/* McPDM registers */
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#define MCPDM_REVISION 0x00
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#define MCPDM_SYSCONFIG 0x10
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#define MCPDM_IRQSTATUS_RAW 0x24
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#define MCPDM_IRQSTATUS 0x28
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#define MCPDM_IRQENABLE_SET 0x2C
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#define MCPDM_IRQENABLE_CLR 0x30
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#define MCPDM_IRQWAKE_EN 0x34
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#define MCPDM_DMAENABLE_SET 0x38
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#define MCPDM_DMAENABLE_CLR 0x3C
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#define MCPDM_DMAWAKEEN 0x40
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#define MCPDM_CTRL 0x44
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#define MCPDM_DN_DATA 0x48
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#define MCPDM_UP_DATA 0x4C
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#define MCPDM_FIFO_CTRL_DN 0x50
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#define MCPDM_FIFO_CTRL_UP 0x54
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#define MCPDM_DN_OFFSET 0x58
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/*
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* MCPDM_IRQ bit fields
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* IRQSTATUS_RAW, IRQSTATUS, IRQENABLE_SET, IRQENABLE_CLR
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*/
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#define MCPDM_DN_IRQ (1 << 0)
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#define MCPDM_DN_IRQ_EMPTY (1 << 1)
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#define MCPDM_DN_IRQ_ALMST_EMPTY (1 << 2)
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#define MCPDM_DN_IRQ_FULL (1 << 3)
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#define MCPDM_UP_IRQ (1 << 8)
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#define MCPDM_UP_IRQ_EMPTY (1 << 9)
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#define MCPDM_UP_IRQ_ALMST_FULL (1 << 10)
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#define MCPDM_UP_IRQ_FULL (1 << 11)
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#define MCPDM_DOWNLINK_IRQ_MASK 0x00F
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#define MCPDM_UPLINK_IRQ_MASK 0xF00
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/*
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* MCPDM_DMAENABLE bit fields
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*/
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#define DMA_DN_ENABLE 0x1
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#define DMA_UP_ENABLE 0x2
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/*
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* MCPDM_CTRL bit fields
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*/
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#define PDM_UP1_EN 0x0001
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#define PDM_UP2_EN 0x0002
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#define PDM_UP3_EN 0x0004
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#define PDM_DN1_EN 0x0008
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#define PDM_DN2_EN 0x0010
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#define PDM_DN3_EN 0x0020
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#define PDM_DN4_EN 0x0040
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#define PDM_DN5_EN 0x0080
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#define PDMOUTFORMAT 0x0100
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#define CMD_INT 0x0200
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#define STATUS_INT 0x0400
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#define SW_UP_RST 0x0800
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#define SW_DN_RST 0x1000
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#define PDM_UP_MASK 0x007
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#define PDM_DN_MASK 0x0F8
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#define PDM_CMD_MASK 0x200
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#define PDM_STATUS_MASK 0x400
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#define PDMOUTFORMAT_LJUST (0 << 8)
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#define PDMOUTFORMAT_RJUST (1 << 8)
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/*
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* MCPDM_FIFO_CTRL bit fields
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*/
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#define UP_THRES_MAX 0xF
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#define DN_THRES_MAX 0xF
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/*
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* MCPDM_DN_OFFSET bit fields
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*/
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#define DN_OFST_RX1_EN 0x0001
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#define DN_OFST_RX2_EN 0x0100
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#define DN_OFST_RX1 1
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#define DN_OFST_RX2 9
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#define DN_OFST_MAX 0x1F
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#define MCPDM_UPLINK 1
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#define MCPDM_DOWNLINK 2
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struct omap_mcpdm_link {
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int irq_mask;
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int threshold;
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int format;
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int channels;
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};
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struct omap_mcpdm_platform_data {
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unsigned long phys_base;
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u16 irq;
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};
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struct omap_mcpdm {
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struct device *dev;
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unsigned long phys_base;
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void __iomem *io_base;
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u8 free;
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int irq;
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spinlock_t lock;
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struct omap_mcpdm_platform_data *pdata;
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struct clk *clk;
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struct omap_mcpdm_link *downlink;
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struct omap_mcpdm_link *uplink;
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struct completion irq_completion;
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int dn_channels;
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int up_channels;
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};
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extern void omap_mcpdm_start(int stream);
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extern void omap_mcpdm_stop(int stream);
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extern int omap_mcpdm_capture_open(struct omap_mcpdm_link *uplink);
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extern int omap_mcpdm_playback_open(struct omap_mcpdm_link *downlink);
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extern int omap_mcpdm_capture_close(struct omap_mcpdm_link *uplink);
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extern int omap_mcpdm_playback_close(struct omap_mcpdm_link *downlink);
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extern int omap_mcpdm_request(void);
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extern void omap_mcpdm_free(void);
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extern int omap_mcpdm_set_offset(int offset1, int offset2);
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