206 lines
8.9 KiB
Plaintext
206 lines
8.9 KiB
Plaintext
MPC5200 Device Tree Bindings
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----------------------------
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(c) 2006-2009 Secret Lab Technologies Ltd
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Grant Likely <grant.likely@secretlab.ca>
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Naming conventions
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------------------
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For mpc5200 on-chip devices, the format for each compatible value is
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<chip>-<device>[-<mode>]. The OS should be able to match a device driver
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to the device based solely on the compatible value. If two drivers
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match on the compatible list; the 'most compatible' driver should be
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selected.
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The split between the MPC5200 and the MPC5200B leaves a bit of a
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conundrum. How should the compatible property be set up to provide
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maximum compatibility information; but still accurately describe the
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chip? For the MPC5200; the answer is easy. Most of the SoC devices
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originally appeared on the MPC5200. Since they didn't exist anywhere
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else; the 5200 compatible properties will contain only one item;
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"fsl,mpc5200-<device>".
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The 5200B is almost the same as the 5200, but not quite. It fixes
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silicon bugs and it adds a small number of enhancements. Most of the
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devices either provide exactly the same interface as on the 5200. A few
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devices have extra functions but still have a backwards compatible mode.
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To express this information as completely as possible, 5200B device trees
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should have two items in the compatible list:
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compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
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It is *strongly* recommended that 5200B device trees follow this convention
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(instead of only listing the base mpc5200 item).
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ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
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ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
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Modal devices, like PSCs, also append the configured function to the
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end of the compatible field. ie. A PSC in i2s mode would specify
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"fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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avoid naming conflicts with non-psc devices providing the same
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function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
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the mpc5200 simple spi device and a PSC spi mode respectively.
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At the time of writing, exact chip may be either 'fsl,mpc5200' or
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'fsl,mpc5200b'.
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The soc node
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------------
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This node describes the on chip SOC peripherals. Every mpc5200 based
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board will have this node, and as such there is a common naming
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convention for SOC devices.
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Required properties:
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name description
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---- -----------
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ranges Memory range of the internal memory mapped registers.
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Should be <0 [baseaddr] 0xc000>
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reg Should be <[baseaddr] 0x100>
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compatible mpc5200: "fsl,mpc5200-immr"
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mpc5200b: "fsl,mpc5200b-immr"
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system-frequency 'fsystem' frequency in Hz; XLB, IPB, USB and PCI
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clocks are derived from the fsystem clock.
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bus-frequency IPB bus frequency in Hz. Clock rate
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used by most of the soc devices.
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soc child nodes
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---------------
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Any on chip SOC devices available to Linux must appear as soc5200 child nodes.
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Note: The tables below show the value for the mpc5200. A mpc5200b device
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tree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form.
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Required soc5200 child nodes:
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name compatible Description
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---- ---------- -----------
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cdm@<addr> fsl,mpc5200-cdm Clock Distribution
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interrupt-controller@<addr> fsl,mpc5200-pic need an interrupt
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controller to boot
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bestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller
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Recommended soc5200 child nodes; populate as needed for your board
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name compatible Description
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---- ---------- -----------
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timer@<addr> fsl,mpc5200-gpt General purpose timers
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gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller
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gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller
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rtc@<addr> fsl,mpc5200-rtc Real time clock
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mscan@<addr> fsl,mpc5200-mscan CAN bus controller
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pci@<addr> fsl,mpc5200-pci PCI bridge
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serial@<addr> fsl,mpc5200-psc-uart PSC in serial mode
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i2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode
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ac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode
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spi@<addr> fsl,mpc5200-psc-spi PSC in spi mode
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irda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode
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spi@<addr> fsl,mpc5200-spi MPC5200 spi device
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ethernet@<addr> fsl,mpc5200-fec MPC5200 ethernet device
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ata@<addr> fsl,mpc5200-ata IDE ATA interface
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i2c@<addr> fsl,mpc5200-i2c I2C controller
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usb@<addr> fsl,mpc5200-ohci,ohci-be USB controller
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xlb@<addr> fsl,mpc5200-xlb XLB arbitrator
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fsl,mpc5200-gpt nodes
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---------------------
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On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
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design supports the internal wdt, then the device node for GPT0 should
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include the empty property 'fsl,has-wdt'. Note that this does not activate
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the watchdog. The timer will function as a GPT if the timer api is used, and
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it will function as watchdog if the watchdog device is used. The watchdog
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mode has priority over the gpt mode, i.e. if the watchdog is activated, any
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gpt api call to this timer will fail with -EBUSY.
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If you add the property
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fsl,wdt-on-boot = <n>;
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GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
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If n>0, the watchdog is started with a timeout of n seconds. If n=0, the
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configuration of the watchdog is not touched. This is useful in two cases:
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- just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
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- do not touch a configuration assigned by the boot loader which supervises
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the boot process itself.
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The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option.
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An mpc5200-gpt can be used as a single line GPIO controller. To do so,
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add the following properties to the gpt node:
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gpio-controller;
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#gpio-cells = <2>;
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When referencing the GPIO line from another node, the first cell must always
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be zero and the second cell represents the gpio flags and described in the
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gpio device tree binding.
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An mpc5200-gpt can be used as a single line edge sensitive interrupt
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controller. To do so, add the following properties to the gpt node:
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interrupt-controller;
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#interrupt-cells = <1>;
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When referencing the IRQ line from another node, the cell represents the
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sense mode; 1 for edge rising, 2 for edge falling.
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fsl,mpc5200-psc nodes
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---------------------
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The PSCs should include a cell-index which is the index of the PSC in
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hardware. cell-index is used to determine which shared SoC registers to
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use when setting up PSC clocking. cell-index number starts at '0'. ie:
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PSC1 has 'cell-index = <0>'
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PSC4 has 'cell-index = <3>'
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PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in
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i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
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compatible field.
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fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes
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------------------------------------------------
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Each GPIO controller node should have the empty property gpio-controller and
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#gpio-cells set to 2. First cell is the GPIO number which is interpreted
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according to the bit numbers in the GPIO control registers. The second cell
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is for flags which is currently unused.
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fsl,mpc5200-fec nodes
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---------------------
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The FEC node can specify one of the following properties to configure
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the MII link:
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- fsl,7-wire-mode - An empty property that specifies the link uses 7-wire
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mode instead of MII
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- current-speed - Specifies that the MII should be configured for a fixed
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speed. This property should contain two cells. The
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first cell specifies the speed in Mbps and the second
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should be '0' for half duplex and '1' for full duplex
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- phy-handle - Contains a phandle to an Ethernet PHY.
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Interrupt controller (fsl,mpc5200-pic) node
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-------------------------------------------
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The mpc5200 pic binding splits hardware IRQ numbers into two levels. The
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split reflects the layout of the PIC hardware itself, which groups
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interrupts into one of three groups; CRIT, MAIN or PERP. Also, the
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Bestcomm dma engine has it's own set of interrupt sources which are
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cascaded off of peripheral interrupt 0, which the driver interprets as a
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fourth group, SDMA.
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The interrupts property for device nodes using the mpc5200 pic consists
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of three cells; <L1 L2 level>
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L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
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L2 := interrupt number; directly mapped from the value in the
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"ICTL PerStat, MainStat, CritStat Encoded Register"
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level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3]
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For external IRQs, use the following interrupt property values (how to
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specify external interrupts is a frequently asked question):
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External interrupts:
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external irq0: interrupts = <0 0 n>;
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external irq1: interrupts = <1 1 n>;
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external irq2: interrupts = <1 2 n>;
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external irq3: interrupts = <1 3 n>;
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'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low)
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fsl,mpc5200-mscan nodes
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-----------------------
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In addition to the required compatible-, reg- and interrupt-properites, you can
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also specify which clock source shall be used for the controller:
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- fsl,mscan-clock-source- a string describing the clock source. Valid values
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are: "ip" for ip bus clock
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"ref" for reference clock (XTAL)
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"ref" is default in case this property is not
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present.
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