5850dd8f6d
With soft-disabled interrupts in power_save, we can still get external exceptions on Cell, even if we are in pause(0) a.k.a. sleep state. When the CPU really wakes up through the 0x100 (system reset) vector, while we have already started processing the 0x500 (external) exception, we get a panic in unrecoverable_exception() because of the lost state. This occurred in Systemsim for Cell, but as far as I can see, it can theoretically occur on any machine that uses the system reset exception to get out of sleep state. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
134 lines
3.3 KiB
C
134 lines
3.3 KiB
C
/*
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* CBE Pervasive Monitor and Debug
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*
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* (C) Copyright IBM Corporation 2005
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*
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* Authors: Maximino Aguilar (maguilar@us.ibm.com)
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* Michael N. Day (mnday@us.ibm.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#undef DEBUG
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/percpu.h>
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#include <linux/types.h>
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#include <linux/kallsyms.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/pgtable.h>
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#include <asm/reg.h>
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#include "pervasive.h"
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#include "cbe_regs.h"
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static void cbe_power_save(void)
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{
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unsigned long ctrl, thread_switch_control;
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/*
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* We need to hard disable interrupts, but we also need to mark them
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* hard disabled in the PACA so that the local_irq_enable() done by
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* our caller upon return propertly hard enables.
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*/
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hard_irq_disable();
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get_paca()->hard_enabled = 0;
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ctrl = mfspr(SPRN_CTRLF);
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/* Enable DEC and EE interrupt request */
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thread_switch_control = mfspr(SPRN_TSC_CELL);
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thread_switch_control |= TSC_CELL_EE_ENABLE | TSC_CELL_EE_BOOST;
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switch (ctrl & CTRL_CT) {
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case CTRL_CT0:
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thread_switch_control |= TSC_CELL_DEC_ENABLE_0;
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break;
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case CTRL_CT1:
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thread_switch_control |= TSC_CELL_DEC_ENABLE_1;
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break;
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default:
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printk(KERN_WARNING "%s: unknown configuration\n",
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__FUNCTION__);
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break;
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}
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mtspr(SPRN_TSC_CELL, thread_switch_control);
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/*
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* go into low thread priority, medium priority will be
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* restored for us after wake-up.
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*/
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HMT_low();
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/*
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* atomically disable thread execution and runlatch.
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* External and Decrementer exceptions are still handled when the
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* thread is disabled but now enter in cbe_system_reset_exception()
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*/
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ctrl &= ~(CTRL_RUNLATCH | CTRL_TE);
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mtspr(SPRN_CTRLT, ctrl);
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}
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static int cbe_system_reset_exception(struct pt_regs *regs)
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{
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switch (regs->msr & SRR1_WAKEMASK) {
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case SRR1_WAKEEE:
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do_IRQ(regs);
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break;
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case SRR1_WAKEDEC:
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timer_interrupt(regs);
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break;
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case SRR1_WAKEMT:
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break;
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#ifdef CONFIG_CBE_RAS
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case SRR1_WAKESYSERR:
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cbe_system_error_exception(regs);
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break;
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case SRR1_WAKETHERM:
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cbe_thermal_exception(regs);
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break;
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#endif /* CONFIG_CBE_RAS */
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default:
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/* do system reset */
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return 0;
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}
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/* everything handled */
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return 1;
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}
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void __init cbe_pervasive_init(void)
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{
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int cpu;
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if (!cpu_has_feature(CPU_FTR_PAUSE_ZERO))
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return;
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for_each_possible_cpu(cpu) {
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struct cbe_pmd_regs __iomem *regs = cbe_get_cpu_pmd_regs(cpu);
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if (!regs)
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continue;
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/* Enable Pause(0) control bit */
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out_be64(®s->pmcr, in_be64(®s->pmcr) |
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CBE_PMD_PAUSE_ZERO_CONTROL);
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}
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ppc_md.power_save = cbe_power_save;
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ppc_md.system_reset_exception = cbe_system_reset_exception;
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}
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