4c18e77f71
Multiple peripherals in SPEAr share common hardware interrupt lines. This patch adds support for a shared irq layer, which registers hardware irqs by itself and exposes virtual irq numbers to peripherals. Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
98 lines
2.7 KiB
C
98 lines
2.7 KiB
C
/*
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* arch/arm/mach-spear6xx/include/mach/irqs.h
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*
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* IRQ helper macros for SPEAr6xx machine family
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*
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* Copyright (C) 2009 ST Microelectronics
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* Rajeev Kumar<rajeev-dlh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __MACH_IRQS_H
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#define __MACH_IRQS_H
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/* IRQ definitions */
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/* VIC 1 */
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#define IRQ_INTRCOMM_SW_IRQ 0
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#define IRQ_INTRCOMM_CPU_1 1
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#define IRQ_INTRCOMM_CPU_2 2
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#define IRQ_INTRCOMM_RAS2A11_1 3
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#define IRQ_INTRCOMM_RAS2A11_2 4
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#define IRQ_INTRCOMM_RAS2A12_1 5
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#define IRQ_INTRCOMM_RAS2A12_2 6
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#define IRQ_GEN_RAS_0 7
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#define IRQ_GEN_RAS_1 8
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#define IRQ_GEN_RAS_2 9
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#define IRQ_GEN_RAS_3 10
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#define IRQ_GEN_RAS_4 11
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#define IRQ_GEN_RAS_5 12
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#define IRQ_GEN_RAS_6 13
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#define IRQ_GEN_RAS_7 14
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#define IRQ_GEN_RAS_8 15
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#define IRQ_CPU_GPT1_1 16
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#define IRQ_CPU_GPT1_2 17
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#define IRQ_LOCAL_GPIO 18
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#define IRQ_PLL_UNLOCK 19
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#define IRQ_JPEG 20
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#define IRQ_FSMC 21
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#define IRQ_IRDA 22
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#define IRQ_RESERVED 23
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#define IRQ_UART_0 24
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#define IRQ_UART_1 25
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#define IRQ_SSP_1 26
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#define IRQ_SSP_2 27
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#define IRQ_I2C 28
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#define IRQ_GEN_RAS_9 29
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#define IRQ_GEN_RAS_10 30
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#define IRQ_GEN_RAS_11 31
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/* VIC 2 */
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#define IRQ_APPL_GPT1_1 32
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#define IRQ_APPL_GPT1_2 33
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#define IRQ_APPL_GPT2_1 34
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#define IRQ_APPL_GPT2_2 35
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#define IRQ_APPL_GPIO 36
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#define IRQ_APPL_SSP 37
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#define IRQ_APPL_ADC 38
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#define IRQ_APPL_RESERVED 39
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#define IRQ_AHB_EXP_MASTER 40
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#define IRQ_DDR_CONTROLLER 41
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#define IRQ_BASIC_DMA 42
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#define IRQ_BASIC_RESERVED1 43
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#define IRQ_BASIC_SMI 44
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#define IRQ_BASIC_CLCD 45
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#define IRQ_EXP_AHB_1 46
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#define IRQ_EXP_AHB_2 47
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#define IRQ_BASIC_GPT1_1 48
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#define IRQ_BASIC_GPT1_2 49
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#define IRQ_BASIC_RTC 50
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#define IRQ_BASIC_GPIO 51
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#define IRQ_BASIC_WDT 52
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#define IRQ_BASIC_RESERVED 53
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#define IRQ_AHB_EXP_SLAVE 54
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#define IRQ_GMAC_1 55
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#define IRQ_GMAC_2 56
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#define IRQ_USB_DEV 57
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#define IRQ_USB_H_OHCI_0 58
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#define IRQ_USB_H_EHCI_0 59
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#define IRQ_USB_H_OHCI_1 60
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#define IRQ_USB_H_EHCI_1 61
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#define IRQ_EXP_AHB_3 62
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#define IRQ_EXP_AHB_4 63
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#define IRQ_VIC_END 64
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/* GPIO pins virtual irqs */
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#define SPEAR_GPIO_INT_BASE IRQ_VIC_END
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#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE
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#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8)
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#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8)
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#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8)
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#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END)
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#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS)
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#endif /* __MACH_IRQS_H */
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