372 lines
10 KiB
ArmAsm
372 lines
10 KiB
ArmAsm
/*
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* linux/arch/arm/mm/proc-v7.S
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*
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* Copyright (C) 2001 Deep Blue Solutions Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This is the "shell" of the ARMv7 processor support.
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*/
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#include <linux/init.h>
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/asm-offsets.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include "proc-macros.S"
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#ifdef CONFIG_ARM_LPAE
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#include "proc-v7-3level.S"
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#else
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#include "proc-v7-2level.S"
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#endif
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ENTRY(cpu_v7_proc_init)
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mov pc, lr
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ENDPROC(cpu_v7_proc_init)
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ENTRY(cpu_v7_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x1000 @ ...i............
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bic r0, r0, #0x0006 @ .............ca.
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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ENDPROC(cpu_v7_proc_fin)
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/*
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* cpu_v7_reset(loc)
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*
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* Perform a soft reset of the system. Put the CPU into the
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* same state as it would be if it had been reset, and branch
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* to what would be the reset vector.
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*
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* - loc - location to jump to for soft reset
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*
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* This code must be executed using a flat identity mapping with
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* caches disabled.
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*/
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.align 5
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.pushsection .idmap.text, "ax"
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ENTRY(cpu_v7_reset)
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mrc p15, 0, r1, c1, c0, 0 @ ctrl register
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bic r1, r1, #0x1 @ ...............m
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THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
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mcr p15, 0, r1, c1, c0, 0 @ disable MMU
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isb
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mov pc, r0
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ENDPROC(cpu_v7_reset)
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.popsection
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/*
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* cpu_v7_do_idle()
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*
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* Idle the processor (eg, wait for interrupt).
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*
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* IRQs are already disabled.
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*/
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ENTRY(cpu_v7_do_idle)
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dsb @ WFI may enter a low-power mode
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wfi
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mov pc, lr
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ENDPROC(cpu_v7_do_idle)
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ENTRY(cpu_v7_dcache_clean_area)
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#ifndef TLB_CAN_READ_FROM_L1_CACHE
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dcache_line_size r2, r3
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1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
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add r0, r0, r2
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subs r1, r1, r2
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bhi 1b
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dsb
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#endif
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mov pc, lr
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ENDPROC(cpu_v7_dcache_clean_area)
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string cpu_v7_name, "ARMv7 Processor"
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.align
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/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
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.globl cpu_v7_suspend_size
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.equ cpu_v7_suspend_size, 4 * 8
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#ifdef CONFIG_ARM_CPU_SUSPEND
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ENTRY(cpu_v7_do_suspend)
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stmfd sp!, {r4 - r10, lr}
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mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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stmia r0!, {r4 - r5}
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mrc p15, 0, r6, c3, c0, 0 @ Domain ID
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mrc p15, 0, r7, c2, c0, 1 @ TTB 1
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mrc p15, 0, r11, c2, c0, 2 @ TTB control register
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mrc p15, 0, r8, c1, c0, 0 @ Control register
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mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
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mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
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stmia r0, {r6 - r11}
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ldmfd sp!, {r4 - r10, pc}
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ENDPROC(cpu_v7_do_suspend)
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ENTRY(cpu_v7_do_resume)
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mov ip, #0
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mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
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ldmia r0!, {r4 - r5}
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mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
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mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
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ldmia r0, {r6 - r11}
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mcr p15, 0, r6, c3, c0, 0 @ Domain ID
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#ifndef CONFIG_ARM_LPAE
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ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
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ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
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#endif
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mcr p15, 0, r1, c2, c0, 0 @ TTB 0
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mcr p15, 0, r7, c2, c0, 1 @ TTB 1
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mcr p15, 0, r11, c2, c0, 2 @ TTB control register
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mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
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teq r4, r9 @ Is it already set?
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mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
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mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
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ldr r4, =PRRR @ PRRR
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ldr r5, =NMRR @ NMRR
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mcr p15, 0, r4, c10, c2, 0 @ write PRRR
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mcr p15, 0, r5, c10, c2, 1 @ write NMRR
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isb
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dsb
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mov r0, r8 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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#endif
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__CPUINIT
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/*
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* __v7_setup
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*
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* Initialise TLB, Caches, and MMU state ready to switch the MMU
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* on. Return in r0 the new CP15 C1 control register setting.
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*
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* We automatically detect if we have a Harvard cache, and use the
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* Harvard cache control instructions insead of the unified cache
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* control instructions.
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*
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* This should be able to cover all ARMv7 cores.
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*
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* It is assumed that:
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* - cache type register is implemented
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*/
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__v7_ca5mp_setup:
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__v7_ca9mp_setup:
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mov r10, #(1 << 0) @ TLB ops broadcasting
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b 1f
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__v7_ca7mp_setup:
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__v7_ca15mp_setup:
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mov r10, #0
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1:
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#ifdef CONFIG_SMP
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ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
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ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
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tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
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orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
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orreq r0, r0, r10 @ Enable CPU-specific SMP bits
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mcreq p15, 0, r0, c1, c0, 1
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#endif
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__v7_setup:
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adr r12, __v7_setup_stack @ the local stack
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stmia r12, {r0-r5, r7, r9, r11, lr}
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bl v7_flush_dcache_all
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ldmia r12, {r0-r5, r7, r9, r11, lr}
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mrc p15, 0, r0, c0, c0, 0 @ read main ID register
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and r10, r0, #0xff000000 @ ARM?
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teq r10, #0x41000000
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bne 3f
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and r5, r0, #0x00f00000 @ variant
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and r6, r0, #0x0000000f @ revision
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orr r6, r6, r5, lsr #20-4 @ combine variant and revision
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ubfx r0, r0, #4, #12 @ primary part number
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/* Cortex-A8 Errata */
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ldr r10, =0x00000c08 @ Cortex-A8 primary part number
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teq r0, r10
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bne 2f
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#ifdef CONFIG_ARM_ERRATA_430973
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teq r5, #0x00100000 @ only present in r1p*
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 6) @ set IBE to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_458693
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
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orreq r10, r10, #(1 << 5) @ set L1NEON to 1
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orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
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mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
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#endif
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#ifdef CONFIG_ARM_ERRATA_460075
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teq r6, #0x20 @ only present in r2p0
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mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
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tsteq r10, #1 << 22
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orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
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mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
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#endif
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b 3f
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/* Cortex-A9 Errata */
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2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
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teq r0, r10
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bne 3f
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#ifdef CONFIG_ARM_ERRATA_742230
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cmp r6, #0x22 @ only present up to r2p2
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mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrle r10, r10, #1 << 4 @ set bit #4
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mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_742231
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teq r6, #0x20 @ present in r2p0
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teqne r6, #0x21 @ present in r2p1
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teqne r6, #0x22 @ present in r2p2
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 12 @ set bit #12
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orreq r10, r10, #1 << 22 @ set bit #22
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#ifdef CONFIG_ARM_ERRATA_743622
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teq r6, #0x20 @ present in r2p0
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teqne r6, #0x21 @ present in r2p1
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teqne r6, #0x22 @ present in r2p2
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mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orreq r10, r10, #1 << 6 @ set bit #6
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mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
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#endif
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#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
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ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
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ALT_UP_B(1f)
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mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
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orrlt r10, r10, #1 << 11 @ set bit #11
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mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
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1:
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#endif
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3: mov r10, #0
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#ifdef HARVARD_CACHE
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mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
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#endif
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dsb
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#ifdef CONFIG_MMU
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mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
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v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
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ldr r5, =PRRR @ PRRR
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ldr r6, =NMRR @ NMRR
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mcr p15, 0, r5, c10, c2, 0 @ write PRRR
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mcr p15, 0, r6, c10, c2, 1 @ write NMRR
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#endif
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adr r5, v7_crval
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ldmia r5, {r5, r6}
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#ifdef CONFIG_CPU_ENDIAN_BE8
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orr r6, r6, #1 << 25 @ big-endian page tables
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#endif
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#ifdef CONFIG_SWP_EMULATE
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orr r5, r5, #(1 << 10) @ set SW bit in "clear"
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bic r6, r6, #(1 << 10) @ clear it in "mmuset"
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#endif
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mrc p15, 0, r0, c1, c0, 0 @ read control register
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bic r0, r0, r5 @ clear bits them
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orr r0, r0, r6 @ set them
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THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
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mov pc, lr @ return to head.S:__ret
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ENDPROC(__v7_setup)
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.align 2
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__v7_setup_stack:
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.space 4 * 11 @ 11 registers
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__INITDATA
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@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
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define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
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.section ".rodata"
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string cpu_arch_name, "armv7"
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string cpu_elf_name, "v7"
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.align
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.section ".proc.info.init", #alloc, #execinstr
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/*
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* Standard v7 proc info content
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*/
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.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
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ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
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PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
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ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
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PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
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.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
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PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
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W(b) \initfunc
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
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HWCAP_EDSP | HWCAP_TLS | \hwcaps
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.long cpu_v7_name
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.long v7_processor_functions
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.long v7wbi_tlb_fns
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.long v6_user_fns
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.long v7_cache_fns
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.endm
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#ifndef CONFIG_ARM_LPAE
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/*
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* ARM Ltd. Cortex A5 processor.
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*/
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.type __v7_ca5mp_proc_info, #object
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__v7_ca5mp_proc_info:
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.long 0x410fc050
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.long 0xff0ffff0
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__v7_proc __v7_ca5mp_setup
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.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
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/*
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* ARM Ltd. Cortex A7 processor.
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*/
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.type __v7_ca7mp_proc_info, #object
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__v7_ca7mp_proc_info:
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.long 0x410fc070
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.long 0xff0ffff0
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__v7_proc __v7_ca7mp_setup, hwcaps = HWCAP_IDIV
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.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
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/*
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* ARM Ltd. Cortex A9 processor.
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*/
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.type __v7_ca9mp_proc_info, #object
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__v7_ca9mp_proc_info:
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.long 0x410fc090
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.long 0xff0ffff0
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__v7_proc __v7_ca9mp_setup
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.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
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#endif /* CONFIG_ARM_LPAE */
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/*
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* ARM Ltd. Cortex A15 processor.
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*/
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.type __v7_ca15mp_proc_info, #object
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__v7_ca15mp_proc_info:
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.long 0x410fc0f0
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.long 0xff0ffff0
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__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
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.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
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/*
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* Match any ARMv7 processor core.
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*/
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.type __v7_proc_info, #object
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__v7_proc_info:
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.long 0x000f0000 @ Required ID value
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.long 0x000f0000 @ Mask for ID
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__v7_proc __v7_setup
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.size __v7_proc_info, . - __v7_proc_info
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