5be8554875
Default ops are implicit now. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
150 lines
3.6 KiB
C
150 lines
3.6 KiB
C
/*
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* Board setup routines for the GEFanuc C2K board
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*
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* Author: Remi Machet <rmachet@slac.stanford.edu>
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*
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* Originated from prpmc2800.c
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*
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* 2008 (c) Stanford University
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* 2007 (c) MontaVista, Software, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/seq_file.h>
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#include <linux/time.h>
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#include <linux/of.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/system.h>
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#include <asm/time.h>
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#include <mm/mmu_decl.h>
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#include <sysdev/mv64x60.h>
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#define MV64x60_MPP_CNTL_0 0x0000
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#define MV64x60_MPP_CNTL_2 0x0008
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#define MV64x60_GPP_IO_CNTL 0x0000
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#define MV64x60_GPP_LEVEL_CNTL 0x0010
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#define MV64x60_GPP_VALUE_SET 0x0018
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static void __iomem *mv64x60_mpp_reg_base;
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static void __iomem *mv64x60_gpp_reg_base;
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static void __init c2k_setup_arch(void)
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{
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struct device_node *np;
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phys_addr_t paddr;
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const unsigned int *reg;
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/*
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* ioremap mpp and gpp registers in case they are later
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* needed by c2k_reset_board().
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*/
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np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-mpp");
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reg = of_get_property(np, "reg", NULL);
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paddr = of_translate_address(np, reg);
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of_node_put(np);
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mv64x60_mpp_reg_base = ioremap(paddr, reg[1]);
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np = of_find_compatible_node(NULL, NULL, "marvell,mv64360-gpp");
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reg = of_get_property(np, "reg", NULL);
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paddr = of_translate_address(np, reg);
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of_node_put(np);
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mv64x60_gpp_reg_base = ioremap(paddr, reg[1]);
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#ifdef CONFIG_PCI
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mv64x60_pci_init();
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#endif
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}
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static void c2k_reset_board(void)
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{
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u32 temp;
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local_irq_disable();
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temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0);
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temp &= 0xFFFF0FFF;
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out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_0, temp);
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temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
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temp |= 0x00000004;
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
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temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
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temp |= 0x00000004;
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
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temp = in_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2);
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temp &= 0xFFFF0FFF;
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out_le32(mv64x60_mpp_reg_base + MV64x60_MPP_CNTL_2, temp);
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temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL);
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temp |= 0x00080000;
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_LEVEL_CNTL, temp);
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temp = in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL);
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temp |= 0x00080000;
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_IO_CNTL, temp);
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out_le32(mv64x60_gpp_reg_base + MV64x60_GPP_VALUE_SET, 0x00080004);
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}
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static void c2k_restart(char *cmd)
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{
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c2k_reset_board();
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msleep(100);
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panic("restart failed\n");
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}
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#ifdef CONFIG_NOT_COHERENT_CACHE
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#define COHERENCY_SETTING "off"
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#else
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#define COHERENCY_SETTING "on"
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#endif
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void c2k_show_cpuinfo(struct seq_file *m)
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{
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seq_printf(m, "Vendor\t\t: GEFanuc\n");
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seq_printf(m, "coherency\t: %s\n", COHERENCY_SETTING);
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}
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init c2k_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (!of_flat_dt_is_compatible(root, "GEFanuc,C2K"))
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return 0;
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printk(KERN_INFO "Detected a GEFanuc C2K board\n");
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_set_L2CR(0);
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_set_L2CR(L2CR_L2E | L2CR_L2PE | L2CR_L2I);
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return 1;
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}
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define_machine(c2k) {
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.name = "C2K",
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.probe = c2k_probe,
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.setup_arch = c2k_setup_arch,
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.init_early = mv64x60_init_early,
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.show_cpuinfo = c2k_show_cpuinfo,
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.init_IRQ = mv64x60_init_irq,
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.get_irq = mv64x60_get_irq,
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.restart = c2k_restart,
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.calibrate_decr = generic_calibrate_decr,
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};
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