a439fe51a1
The majority of this patch was created by the following script: *** ASM=arch/sparc/include/asm mkdir -p $ASM git mv include/asm-sparc64/ftrace.h $ASM git rm include/asm-sparc64/* git mv include/asm-sparc/* $ASM sed -ie 's/asm-sparc64/asm/g' $ASM/* sed -ie 's/asm-sparc/asm/g' $ASM/* *** The rest was an update of the top-level Makefile to use sparc for header files when sparc64 is being build. And a small fixlet to pick up the correct unistd.h from sparc64 code. Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
81 lines
3.2 KiB
C
81 lines
3.2 KiB
C
/*
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* include/asm/sunbpp.h
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*/
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#ifndef _ASM_SPARC_SUNBPP_H
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#define _ASM_SPARC_SUNBPP_H
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struct bpp_regs {
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/* DMA registers */
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__volatile__ __u32 p_csr; /* DMA Control/Status Register */
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__volatile__ __u32 p_addr; /* Address Register */
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__volatile__ __u32 p_bcnt; /* Byte Count Register */
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__volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
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/* Parallel Port registers */
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__volatile__ __u16 p_hcr; /* Hardware Configuration Register */
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__volatile__ __u16 p_ocr; /* Operation Configuration Register */
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__volatile__ __u8 p_dr; /* Parallel Data Register */
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__volatile__ __u8 p_tcr; /* Transfer Control Register */
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__volatile__ __u8 p_or; /* Output Register */
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__volatile__ __u8 p_ir; /* Input Register */
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__volatile__ __u16 p_icr; /* Interrupt Control Register */
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};
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/* P_HCR. Time is in increments of SBus clock. */
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#define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
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#define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
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#define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
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/* P_OCR. */
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#define P_OCR_MEM_CLR 0x8000
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#define P_OCR_DATA_SRC 0x4000 /* ) */
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#define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
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#define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
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#define P_OCR_ACK_DSEL 0x0800 /* ) */
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#define P_OCR_EN_DIAG 0x0400
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#define P_OCR_BUSY_OP 0x0200 /* Busy operation */
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#define P_OCR_ACK_OP 0x0100 /* Ack operation */
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#define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
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#define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
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#define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
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#define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
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/* P_TCR */
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#define P_TCR_DIR 0x08
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#define P_TCR_BUSY 0x04
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#define P_TCR_ACK 0x02
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#define P_TCR_DS 0x01 /* Strobe */
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/* P_OR */
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#define P_OR_V3 0x20 /* ) */
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#define P_OR_V2 0x10 /* ) on Zebra only */
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#define P_OR_V1 0x08 /* ) */
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#define P_OR_INIT 0x04
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#define P_OR_AFXN 0x02 /* Auto Feed */
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#define P_OR_SLCT_IN 0x01
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/* P_IR */
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#define P_IR_PE 0x04
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#define P_IR_SLCT 0x02
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#define P_IR_ERR 0x01
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/* P_ICR */
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#define P_DS_IRQ 0x8000 /* RW1 */
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#define P_ACK_IRQ 0x4000 /* RW1 */
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#define P_BUSY_IRQ 0x2000 /* RW1 */
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#define P_PE_IRQ 0x1000 /* RW1 */
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#define P_SLCT_IRQ 0x0800 /* RW1 */
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#define P_ERR_IRQ 0x0400 /* RW1 */
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#define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
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#define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
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#define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
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#define P_BUSY_IRQ_EN 0x0040 /* RW */
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#define P_PE_IRP 0x0020 /* RW 1= rising edge */
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#define P_PE_IRQ_EN 0x0010 /* RW */
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#define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
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#define P_SLCT_IRQ_EN 0x0004 /* RW */
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#define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
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#define P_ERR_IRQ_EN 0x0001 /* RW */
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#endif /* !(_ASM_SPARC_SUNBPP_H) */
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