1beb6a7d6c
This adds some very basic support for the new machines, including the Quad G5 (tested), and other new dual core based machines and iMac G5 iSight (untested). This is still experimental ! There is no thermal control yet, there is no proper handing of MSIs, etc.. but it boots, I have all 4 cores up on my machine. Compared to the previous version of this patch, this one adds DART IOMMU support for the U4 chipset and thus should work fine on setups with more than 2Gb of RAM. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
75 lines
2.1 KiB
C
75 lines
2.1 KiB
C
/*
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _POWERPC_SYSDEV_DART_H
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#define _POWERPC_SYSDEV_DART_H
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/* Offset from base to control register */
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#define DART_CNTL 0
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/* Offset from base to exception register */
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#define DART_EXCP_U3 0x10
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/* Offset from base to TLB tag registers */
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#define DART_TAGS_U3 0x1000
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/* U4 registers */
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#define DART_BASE_U4 0x10
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#define DART_SIZE_U4 0x20
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#define DART_EXCP_U4 0x30
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#define DART_TAGS_U4 0x1000
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/* Control Register fields */
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/* U3 registers */
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#define DART_CNTL_U3_BASE_MASK 0xfffff
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#define DART_CNTL_U3_BASE_SHIFT 12
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#define DART_CNTL_U3_FLUSHTLB 0x400
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#define DART_CNTL_U3_ENABLE 0x200
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#define DART_CNTL_U3_SIZE_MASK 0x1ff
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#define DART_CNTL_U3_SIZE_SHIFT 0
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/* U4 registers */
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#define DART_BASE_U4_BASE_MASK 0xffffff
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#define DART_BASE_U4_BASE_SHIFT 0
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#define DART_CNTL_U4_FLUSHTLB 0x20000000
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#define DART_CNTL_U4_ENABLE 0x80000000
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#define DART_SIZE_U4_SIZE_MASK 0x1fff
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#define DART_SIZE_U4_SIZE_SHIFT 0
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#define DART_REG(r) (dart + ((r) >> 2))
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#define DART_IN(r) (in_be32(DART_REG(r)))
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#define DART_OUT(r,v) (out_be32(DART_REG(r), (v)))
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/* size of table in pages */
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/* DART table fields */
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#define DARTMAP_VALID 0x80000000
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#define DARTMAP_RPNMASK 0x00ffffff
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#define DART_PAGE_SHIFT 12
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#define DART_PAGE_SIZE (1 << DART_PAGE_SHIFT)
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#define DART_PAGE_FACTOR (PAGE_SHIFT - DART_PAGE_SHIFT)
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#endif /* _POWERPC_SYSDEV_DART_H */
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