390167efa3
Currently there are several dts that don't specify address or size cells for the muram. This causes dtc to use default values, one of which is an address-cells of two, and this breaks the parsing of the muram ranges, which is assuming an address-cells of one. For example: Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1) Explicitly setting the address and size cells gets it parsed properly and gets rid of the four dtc warnings. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
304 lines
6.7 KiB
Plaintext
304 lines
6.7 KiB
Plaintext
/*
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* MPC832x RDB Device Tree Source
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*
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* Copyright 2007 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/ {
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model = "MPC8323ERDB";
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compatible = "MPC8323ERDB", "MPC832xRDB", "MPC83xxRDB";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet0;
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ethernet1 = &enet1;
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serial0 = &serial0;
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serial1 = &serial1;
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pci0 = &pci0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8323@0 {
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device_type = "cpu";
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reg = <0>;
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d-cache-line-size = <20>; // 32 bytes
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i-cache-line-size = <20>; // 32 bytes
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d-cache-size = <4000>; // L1, 16K
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i-cache-size = <4000>; // L1, 16K
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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memory {
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device_type = "memory";
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reg = <00000000 04000000>;
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};
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soc8323@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges = <0 e0000000 00100000>;
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reg = <e0000000 00000200>;
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bus-frequency = <0>;
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wdt@200 {
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device_type = "watchdog";
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compatible = "mpc83xx_wdt";
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reg = <200 100>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl-i2c";
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reg = <3000 100>;
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interrupts = <e 8>;
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interrupt-parent = <&pic>;
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dfsrr;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4500 100>;
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clock-frequency = <0>;
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interrupts = <9 8>;
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interrupt-parent = <&pic>;
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};
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serial1: serial@4600 {
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cell-index = <1>;
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device_type = "serial";
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compatible = "ns16550";
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reg = <4600 100>;
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clock-frequency = <0>;
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interrupts = <a 8>;
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interrupt-parent = <&pic>;
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};
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crypto@30000 {
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device_type = "crypto";
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model = "SEC2";
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compatible = "talitos";
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reg = <30000 7000>;
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interrupts = <b 8>;
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interrupt-parent = <&pic>;
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/* Rev. 2.2 */
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num-channels = <1>;
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channel-fifo-len = <18>;
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exec-units-mask = <0000004c>;
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descriptor-types-mask = <0122003f>;
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};
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pic:pic@700 {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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reg = <700 100>;
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device_type = "ipic";
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};
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par_io@1400 {
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reg = <1400 100>;
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device_type = "par_io";
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num-ports = <7>;
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ucc2pio:ucc_pin@02 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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3 4 3 0 2 0 /* MDIO */
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3 5 1 0 2 0 /* MDC */
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3 15 2 0 1 0 /* RX_CLK (CLK16) */
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3 17 2 0 1 0 /* TX_CLK (CLK3) */
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0 12 1 0 1 0 /* TxD0 */
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0 13 1 0 1 0 /* TxD1 */
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0 14 1 0 1 0 /* TxD2 */
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0 15 1 0 1 0 /* TxD3 */
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0 16 2 0 1 0 /* RxD0 */
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0 17 2 0 1 0 /* RxD1 */
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0 18 2 0 1 0 /* RxD2 */
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0 19 2 0 1 0 /* RxD3 */
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0 1a 2 0 1 0 /* RX_ER */
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0 1b 1 0 1 0 /* TX_ER */
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0 1c 2 0 1 0 /* RX_DV */
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0 1d 2 0 1 0 /* COL */
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0 1e 1 0 1 0 /* TX_EN */
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0 1f 2 0 1 0>; /* CRS */
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};
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ucc3pio:ucc_pin@03 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 d 2 0 1 0 /* RX_CLK (CLK9) */
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3 18 2 0 1 0 /* TX_CLK (CLK10) */
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1 0 1 0 1 0 /* TxD0 */
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1 1 1 0 1 0 /* TxD1 */
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1 2 1 0 1 0 /* TxD2 */
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1 3 1 0 1 0 /* TxD3 */
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1 4 2 0 1 0 /* RxD0 */
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1 5 2 0 1 0 /* RxD1 */
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1 6 2 0 1 0 /* RxD2 */
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1 7 2 0 1 0 /* RxD3 */
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1 8 2 0 1 0 /* RX_ER */
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1 9 1 0 1 0 /* TX_ER */
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1 a 2 0 1 0 /* RX_DV */
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1 b 2 0 1 0 /* COL */
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1 c 1 0 1 0 /* TX_EN */
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1 d 2 0 1 0>; /* CRS */
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};
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};
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};
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qe@e0100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "qe";
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compatible = "fsl,qe";
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ranges = <0 e0100000 00100000>;
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reg = <e0100000 480>;
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brg-frequency = <0>;
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bus-frequency = <BCD3D80>;
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0 00010000 00004000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0 4000>;
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};
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};
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spi@4c0 {
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cell-index = <0>;
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compatible = "fsl,spi";
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reg = <4c0 40>;
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interrupts = <2>;
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interrupt-parent = <&qeic>;
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mode = "cpu-qe";
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};
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spi@500 {
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cell-index = <1>;
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compatible = "fsl,spi";
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reg = <500 40>;
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interrupts = <1>;
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interrupt-parent = <&qeic>;
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mode = "cpu";
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};
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enet0: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <2>;
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device-id = <2>;
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reg = <3000 200>;
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interrupts = <21>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk16";
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tx-clock-name = "clk3";
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phy-handle = <&phy00>;
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pio-handle = <&ucc2pio>;
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};
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enet1: ucc@2200 {
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device_type = "network";
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compatible = "ucc_geth";
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model = "UCC";
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cell-index = <3>;
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device-id = <3>;
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reg = <2200 200>;
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interrupts = <22>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "clk9";
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tx-clock-name = "clk10";
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phy-handle = <&phy04>;
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pio-handle = <&ucc3pio>;
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};
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mdio@3120 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <3120 18>;
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compatible = "fsl,ucc-mdio";
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phy00:ethernet-phy@00 {
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interrupt-parent = <&pic>;
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interrupts = <0>;
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reg = <0>;
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device_type = "ethernet-phy";
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};
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phy04:ethernet-phy@04 {
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interrupt-parent = <&pic>;
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interrupts = <0>;
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reg = <4>;
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device_type = "ethernet-phy";
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};
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};
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qeic:interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <80 80>;
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big-endian;
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interrupts = <20 8 21 8>; //high:32 low:33
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interrupt-parent = <&pic>;
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};
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};
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pci0: pci@e0008500 {
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cell-index = <1>;
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x10 AD16 (USB) */
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8000 0 0 1 &pic 11 8
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/* IDSEL 0x11 AD17 (Mini1)*/
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8800 0 0 1 &pic 12 8
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8800 0 0 2 &pic 13 8
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8800 0 0 3 &pic 14 8
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8800 0 0 4 &pic 30 8
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/* IDSEL 0x12 AD18 (PCI/Mini2) */
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9000 0 0 1 &pic 13 8
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9000 0 0 2 &pic 14 8
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9000 0 0 3 &pic 30 8
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9000 0 0 4 &pic 11 8>;
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interrupt-parent = <&pic>;
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interrupts = <42 8>;
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bus-range = <0 0>;
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ranges = <42000000 0 80000000 80000000 0 10000000
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02000000 0 90000000 90000000 0 10000000
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01000000 0 d0000000 d0000000 0 04000000>;
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clock-frequency = <0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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reg = <e0008500 100>;
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compatible = "fsl,mpc8349-pci";
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device_type = "pci";
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};
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};
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