fee3c55d7f
Problem arise when is incopatibility between kernel/dts/pvr and kernel tries to announce it. Early printk device (uartlite in our case) was in TLB 2 and when kernel extract DTB it necessary to allocate at least one TLB at the end of memory. First free TLB was number two where was early printk. But checking mechanism (kernel/dts/pvr) was after extrahing but TLB 2 was different. This caused that kernel hung up. Moving early printk device to TLB 63 solve it and we don't protect it which means that we can use early_printk messages only for initial parts of kernel then we rewrite TLB 63. Reported-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Michal Simek <monstr@monstr.eu>
121 lines
2.4 KiB
ArmAsm
121 lines
2.4 KiB
ArmAsm
/*
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* Miscellaneous low-level MMU functions.
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*
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* Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2008-2009 PetaLogix
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* Copyright (C) 2007 Xilinx, Inc. All rights reserved.
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*
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* Derived from arch/ppc/kernel/misc.S
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*/
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#include <linux/linkage.h>
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#include <linux/sys.h>
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#include <asm/unistd.h>
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#include <linux/errno.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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.text
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/*
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* Flush MMU TLB
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*
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* We avoid flushing the pinned 0, 1 and possibly 2 entries.
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*/
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.globl _tlbia;
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.align 4;
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_tlbia:
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addik r12, r0, 63 /* flush all entries (63 - 3) */
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/* isync */
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_tlbia_1:
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mts rtlbx, r12
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nop
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mts rtlbhi, r0 /* flush: ensure V is clear */
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nop
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addik r11, r12, -2
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bneid r11, _tlbia_1 /* loop for all entries */
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addik r12, r12, -1
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/* sync */
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rtsd r15, 8
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nop
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/*
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* Flush MMU TLB for a particular address (in r5)
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*/
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.globl _tlbie;
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.align 4;
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_tlbie:
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mts rtlbsx, r5 /* look up the address in TLB */
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nop
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mfs r12, rtlbx /* Retrieve index */
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nop
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blti r12, _tlbie_1 /* Check if found */
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mts rtlbhi, r0 /* flush: ensure V is clear */
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nop
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_tlbie_1:
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rtsd r15, 8
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nop
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/*
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* Allocate TLB entry for early console
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*/
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.globl early_console_reg_tlb_alloc;
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.align 4;
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early_console_reg_tlb_alloc:
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/*
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* Load a TLB entry for the UART, so that microblaze_progress() can use
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* the UARTs nice and early. We use a 4k real==virtual mapping.
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*/
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ori r4, r0, 63
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mts rtlbx, r4 /* TLB slot 2 */
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or r4,r5,r0
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andi r4,r4,0xfffff000
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ori r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
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andi r5,r5,0xfffff000
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ori r5,r5,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
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mts rtlblo,r4 /* Load the data portion of the entry */
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nop
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mts rtlbhi,r5 /* Load the tag portion of the entry */
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nop
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rtsd r15, 8
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nop
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/*
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* Copy a whole page (4096 bytes).
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*/
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#define COPY_16_BYTES \
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lwi r7, r6, 0; \
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lwi r8, r6, 4; \
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lwi r9, r6, 8; \
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lwi r10, r6, 12; \
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swi r7, r5, 0; \
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swi r8, r5, 4; \
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swi r9, r5, 8; \
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swi r10, r5, 12
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/* FIXME DCACHE_LINE_BYTES (CONFIG_XILINX_MICROBLAZE0_DCACHE_LINE_LEN * 4)*/
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#define DCACHE_LINE_BYTES (4 * 4)
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.globl copy_page;
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.align 4;
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copy_page:
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ori r11, r0, (PAGE_SIZE/DCACHE_LINE_BYTES) - 1
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_copy_page_loop:
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COPY_16_BYTES
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#if DCACHE_LINE_BYTES >= 32
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COPY_16_BYTES
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#endif
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addik r6, r6, DCACHE_LINE_BYTES
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addik r5, r5, DCACHE_LINE_BYTES
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bneid r11, _copy_page_loop
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addik r11, r11, -1
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rtsd r15, 8
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nop
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