389eda15e0
Support clk in gpio driver. There's no gpio clock in PXA25x and PXA27x. So use dummy clk instead. And move the gpio edge initialization into gpio driver for arch-mmp. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com>
470 lines
12 KiB
C
470 lines
12 KiB
C
/*
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* linux/arch/arm/mach-pxa/pxa27x.c
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*
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* Author: Nicolas Pitre
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* Created: Nov 05, 2002
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* Copyright: MontaVista Software Inc.
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*
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* Code specific to PXA27x aka Bulverde.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/gpio.h>
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#include <linux/gpio-pxa.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/platform_device.h>
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#include <linux/syscore_ops.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/i2c/pxa-i2c.h>
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#include <linux/gpio.h>
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#include <asm/mach/map.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/suspend.h>
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#include <mach/irqs.h>
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#include <mach/pxa27x.h>
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#include <mach/reset.h>
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#include <mach/ohci.h>
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#include <mach/pm.h>
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#include <mach/dma.h>
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#include <mach/smemc.h>
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#include "generic.h"
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#include "devices.h"
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#include "clock.h"
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void pxa27x_clear_otgph(void)
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{
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if (cpu_is_pxa27x() && (PSSR & PSSR_OTGPH))
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PSSR |= PSSR_OTGPH;
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}
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EXPORT_SYMBOL(pxa27x_clear_otgph);
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static unsigned long ac97_reset_config[] = {
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GPIO113_GPIO,
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GPIO113_AC97_nRESET,
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GPIO95_GPIO,
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GPIO95_AC97_nRESET,
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};
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void pxa27x_assert_ac97reset(int reset_gpio, int on)
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{
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if (reset_gpio == 113)
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pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
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&ac97_reset_config[1], 1);
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if (reset_gpio == 95)
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pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
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&ac97_reset_config[3], 1);
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}
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EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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/*
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* Get the clock frequency as reflected by CCSR and the turbo flag.
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* We assume these values have been applied via a fcs.
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* If info is not 0 we also display the current settings.
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*/
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unsigned int pxa27x_get_clk_frequency_khz(int info)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M, n2, N, S;
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int cccr_a, t, ht, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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t = clkcfg & (1 << 0);
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ht = clkcfg & (1 << 2);
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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n2 = (ccsr>>7) & 0xf;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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N = (L * n2) / 2;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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S = (b) ? L : (L/2);
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if (info) {
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printk( KERN_INFO "Run Mode clock: %d.%02dMHz (*%d)\n",
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L / 1000000, (L % 1000000) / 10000, l );
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printk( KERN_INFO "Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
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N / 1000000, (N % 1000000)/10000, n2 / 2, (n2 % 2)*5,
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(t) ? "" : "in" );
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printk( KERN_INFO "Memory clock: %d.%02dMHz (/%d)\n",
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M / 1000000, (M % 1000000) / 10000, m );
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printk( KERN_INFO "System bus clock: %d.%02dMHz \n",
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S / 1000000, (S % 1000000) / 10000 );
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}
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return (t) ? (N/1000) : (L/1000);
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}
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/*
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* Return the current mem clock frequency as reflected by CCCR[A], B, and L
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*/
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static unsigned long clk_pxa27x_mem_getrate(struct clk *clk)
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{
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unsigned long ccsr, clkcfg;
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unsigned int l, L, m, M;
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int cccr_a, b;
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ccsr = CCSR;
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cccr_a = CCCR & (1 << 25);
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/* Read clkcfg register: it has turbo, b, half-turbo (and f) */
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asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg) );
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b = clkcfg & (1 << 3);
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l = ccsr & 0x1f;
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m = (l <= 10) ? 1 : (l <= 20) ? 2 : 4;
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L = l * BASE_CLK;
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M = (!cccr_a) ? (L/m) : ((b) ? L : (L/2));
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return M;
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}
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static const struct clkops clk_pxa27x_mem_ops = {
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.enable = clk_dummy_enable,
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.disable = clk_dummy_disable,
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.getrate = clk_pxa27x_mem_getrate,
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};
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/*
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* Return the current LCD clock frequency in units of 10kHz as
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*/
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static unsigned int pxa27x_get_lcdclk_frequency_10khz(void)
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{
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unsigned long ccsr;
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unsigned int l, L, k, K;
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ccsr = CCSR;
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l = ccsr & 0x1f;
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k = (l <= 7) ? 1 : (l <= 16) ? 2 : 4;
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L = l * BASE_CLK;
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K = L / k;
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return (K / 10000);
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}
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static unsigned long clk_pxa27x_lcd_getrate(struct clk *clk)
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{
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return pxa27x_get_lcdclk_frequency_10khz() * 10000;
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}
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static const struct clkops clk_pxa27x_lcd_ops = {
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.enable = clk_pxa2xx_cken_enable,
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.disable = clk_pxa2xx_cken_disable,
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.getrate = clk_pxa27x_lcd_getrate,
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};
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static DEFINE_PXA2_CKEN(pxa27x_ffuart, FFUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_btuart, BTUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_stuart, STUART, 14857000, 1);
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static DEFINE_PXA2_CKEN(pxa27x_i2s, I2S, 14682000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_i2c, I2C, 32842000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usb, USB, 48000000, 5);
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static DEFINE_PXA2_CKEN(pxa27x_mmc, MMC, 19500000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ficp, FICP, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usbhost, USBHOST, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwri2c, PWRI2C, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_keypad, KEYPAD, 32768, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp1, SSP1, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp2, SSP2, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ssp3, SSP3, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwm0, PWM0, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_pwm1, PWM1, 13000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ac97, AC97, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_ac97conf, AC97CONF, 24576000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_msl, MSL, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_usim, USIM, 48000000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_memstk, MEMSTK, 19500000, 0);
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static DEFINE_PXA2_CKEN(pxa27x_im, IM, 0, 0);
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static DEFINE_PXA2_CKEN(pxa27x_memc, MEMC, 0, 0);
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static DEFINE_CK(pxa27x_lcd, LCD, &clk_pxa27x_lcd_ops);
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static DEFINE_CK(pxa27x_camera, CAMERA, &clk_pxa27x_lcd_ops);
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static DEFINE_CLK(pxa27x_mem, &clk_pxa27x_mem_ops, 0, 0);
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static struct clk_lookup pxa27x_clkregs[] = {
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INIT_CLKREG(&clk_pxa27x_lcd, "pxa2xx-fb", NULL),
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INIT_CLKREG(&clk_pxa27x_camera, "pxa27x-camera.0", NULL),
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INIT_CLKREG(&clk_pxa27x_ffuart, "pxa2xx-uart.0", NULL),
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INIT_CLKREG(&clk_pxa27x_btuart, "pxa2xx-uart.1", NULL),
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INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-uart.2", NULL),
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INIT_CLKREG(&clk_pxa27x_i2s, "pxa2xx-i2s", NULL),
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INIT_CLKREG(&clk_pxa27x_i2c, "pxa2xx-i2c.0", NULL),
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INIT_CLKREG(&clk_pxa27x_usb, "pxa27x-udc", NULL),
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INIT_CLKREG(&clk_pxa27x_mmc, "pxa2xx-mci.0", NULL),
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INIT_CLKREG(&clk_pxa27x_stuart, "pxa2xx-ir", "UARTCLK"),
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INIT_CLKREG(&clk_pxa27x_ficp, "pxa2xx-ir", "FICPCLK"),
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INIT_CLKREG(&clk_pxa27x_usbhost, "pxa27x-ohci", NULL),
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INIT_CLKREG(&clk_pxa27x_pwri2c, "pxa2xx-i2c.1", NULL),
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INIT_CLKREG(&clk_pxa27x_keypad, "pxa27x-keypad", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp1, "pxa27x-ssp.0", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp2, "pxa27x-ssp.1", NULL),
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INIT_CLKREG(&clk_pxa27x_ssp3, "pxa27x-ssp.2", NULL),
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INIT_CLKREG(&clk_pxa27x_pwm0, "pxa27x-pwm.0", NULL),
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INIT_CLKREG(&clk_pxa27x_pwm1, "pxa27x-pwm.1", NULL),
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INIT_CLKREG(&clk_pxa27x_ac97, NULL, "AC97CLK"),
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INIT_CLKREG(&clk_pxa27x_ac97conf, NULL, "AC97CONFCLK"),
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INIT_CLKREG(&clk_pxa27x_msl, NULL, "MSLCLK"),
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INIT_CLKREG(&clk_pxa27x_usim, NULL, "USIMCLK"),
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INIT_CLKREG(&clk_pxa27x_memstk, NULL, "MSTKCLK"),
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INIT_CLKREG(&clk_pxa27x_im, NULL, "IMCLK"),
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INIT_CLKREG(&clk_pxa27x_memc, NULL, "MEMCLK"),
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INIT_CLKREG(&clk_pxa27x_mem, "pxa2xx-pcmcia", NULL),
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INIT_CLKREG(&clk_dummy, "pxa-gpio", NULL),
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};
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#ifdef CONFIG_PM
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#define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
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#define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
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/*
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* allow platforms to override default PWRMODE setting used for PM_SUSPEND_MEM
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*/
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static unsigned int pwrmode = PWRMODE_SLEEP;
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int __init pxa27x_set_pwrmode(unsigned int mode)
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{
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switch (mode) {
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case PWRMODE_SLEEP:
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case PWRMODE_DEEPSLEEP:
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pwrmode = mode;
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return 0;
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}
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return -EINVAL;
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}
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/*
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* List of global PXA peripheral registers to preserve.
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* More ones like CP and general purpose register values are preserved
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* with the stack pointer in sleep.S.
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*/
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enum {
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SLEEP_SAVE_PSTR,
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SLEEP_SAVE_MDREFR,
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SLEEP_SAVE_PCFR,
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SLEEP_SAVE_COUNT
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};
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void pxa27x_cpu_pm_save(unsigned long *sleep_save)
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{
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sleep_save[SLEEP_SAVE_MDREFR] = __raw_readl(MDREFR);
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SAVE(PCFR);
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SAVE(PSTR);
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}
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void pxa27x_cpu_pm_restore(unsigned long *sleep_save)
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{
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__raw_writel(sleep_save[SLEEP_SAVE_MDREFR], MDREFR);
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RESTORE(PCFR);
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PSSR = PSSR_RDH | PSSR_PH;
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RESTORE(PSTR);
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}
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void pxa27x_cpu_pm_enter(suspend_state_t state)
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{
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extern void pxa_cpu_standby(void);
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#ifndef CONFIG_IWMMXT
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u64 acc0;
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asm volatile("mra %Q0, %R0, acc0" : "=r" (acc0));
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#endif
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/* ensure voltage-change sequencer not initiated, which hangs */
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PCFR &= ~PCFR_FVC;
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/* Clear edge-detect status register. */
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PEDR = 0xDF12FE1B;
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/* Clear reset status */
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RCSR = RCSR_HWR | RCSR_WDR | RCSR_SMR | RCSR_GPR;
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switch (state) {
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case PM_SUSPEND_STANDBY:
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pxa_cpu_standby();
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break;
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case PM_SUSPEND_MEM:
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cpu_suspend(pwrmode, pxa27x_finish_suspend);
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#ifndef CONFIG_IWMMXT
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asm volatile("mar acc0, %Q0, %R0" : "=r" (acc0));
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#endif
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break;
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}
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}
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static int pxa27x_cpu_pm_valid(suspend_state_t state)
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{
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return state == PM_SUSPEND_MEM || state == PM_SUSPEND_STANDBY;
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}
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static int pxa27x_cpu_pm_prepare(void)
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{
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/* set resume return address */
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PSPR = virt_to_phys(cpu_resume);
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return 0;
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}
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static void pxa27x_cpu_pm_finish(void)
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{
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/* ensure not to come back here if it wasn't intended */
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PSPR = 0;
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}
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static struct pxa_cpu_pm_fns pxa27x_cpu_pm_fns = {
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.save_count = SLEEP_SAVE_COUNT,
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.save = pxa27x_cpu_pm_save,
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.restore = pxa27x_cpu_pm_restore,
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.valid = pxa27x_cpu_pm_valid,
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.enter = pxa27x_cpu_pm_enter,
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.prepare = pxa27x_cpu_pm_prepare,
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.finish = pxa27x_cpu_pm_finish,
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};
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static void __init pxa27x_init_pm(void)
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{
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pxa_cpu_pm_fns = &pxa27x_cpu_pm_fns;
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}
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#else
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static inline void pxa27x_init_pm(void) {}
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#endif
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/* PXA27x: Various gpios can issue wakeup events. This logic only
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* handles the simple cases, not the WEMUX2 and WEMUX3 options
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*/
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static int pxa27x_set_wake(struct irq_data *d, unsigned int on)
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{
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int gpio = pxa_irq_to_gpio(d->irq);
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uint32_t mask;
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if (gpio >= 0 && gpio < 128)
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return gpio_set_wake(gpio, on);
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if (d->irq == IRQ_KEYPAD)
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return keypad_set_wake(on);
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switch (d->irq) {
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case IRQ_RTCAlrm:
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mask = PWER_RTC;
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break;
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case IRQ_USB:
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mask = 1u << 26;
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break;
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default:
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return -EINVAL;
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}
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if (on)
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PWER |= mask;
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else
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PWER &=~mask;
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return 0;
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}
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void __init pxa27x_init_irq(void)
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{
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pxa_init_irq(34, pxa27x_set_wake);
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}
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static struct map_desc pxa27x_io_desc[] __initdata = {
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{ /* Mem Ctl */
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.virtual = (unsigned long)SMEMC_VIRT,
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.pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE),
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.length = 0x00200000,
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.type = MT_DEVICE
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}, { /* IMem ctl */
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.virtual = 0xfe000000,
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.pfn = __phys_to_pfn(0x58000000),
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.length = 0x00100000,
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.type = MT_DEVICE
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},
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};
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void __init pxa27x_map_io(void)
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{
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pxa_map_io();
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iotable_init(ARRAY_AND_SIZE(pxa27x_io_desc));
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pxa27x_get_clk_frequency_khz(1);
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}
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/*
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* device registration specific to PXA27x.
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*/
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void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
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{
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local_irq_disable();
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PCFR |= PCFR_PI2CEN;
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local_irq_enable();
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pxa_register_device(&pxa27x_device_i2c_power, info);
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}
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static struct platform_device *devices[] __initdata = {
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&pxa_device_gpio,
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&pxa27x_device_udc,
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&pxa_device_pmu,
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&pxa_device_i2s,
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&pxa_device_asoc_ssp1,
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&pxa_device_asoc_ssp2,
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&pxa_device_asoc_ssp3,
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&pxa_device_asoc_platform,
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&sa1100_device_rtc,
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&pxa_device_rtc,
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&pxa27x_device_ssp1,
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&pxa27x_device_ssp2,
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&pxa27x_device_ssp3,
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&pxa27x_device_pwm0,
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&pxa27x_device_pwm1,
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};
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static int __init pxa27x_init(void)
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{
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int ret = 0;
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if (cpu_is_pxa27x()) {
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reset_status = RCSR;
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clkdev_add_table(pxa27x_clkregs, ARRAY_SIZE(pxa27x_clkregs));
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if ((ret = pxa_init_dma(IRQ_DMA, 32)))
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return ret;
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pxa27x_init_pm();
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register_syscore_ops(&pxa_irq_syscore_ops);
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register_syscore_ops(&pxa2xx_mfp_syscore_ops);
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register_syscore_ops(&pxa_gpio_syscore_ops);
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register_syscore_ops(&pxa2xx_clock_syscore_ops);
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ret = platform_add_devices(devices, ARRAY_SIZE(devices));
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}
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return ret;
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}
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postcore_initcall(pxa27x_init);
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