1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
264 lines
7.0 KiB
C
264 lines
7.0 KiB
C
/**
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* @file arch/alpha/oprofile/op_model_ev67.c
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*
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* @remark Copyright 2002 OProfile authors
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* @remark Read the file COPYING
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*
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* @author Richard Henderson <rth@twiddle.net>
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* @author Falk Hueffner <falk@debian.org>
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*/
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#include <linux/oprofile.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <asm/ptrace.h>
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#include <asm/system.h>
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#include "op_impl.h"
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/* Compute all of the registers in preparation for enabling profiling. */
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static void
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ev67_reg_setup(struct op_register_config *reg,
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struct op_counter_config *ctr,
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struct op_system_config *sys)
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{
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unsigned long ctl, reset, need_reset, i;
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/* Select desired events. */
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ctl = 1UL << 4; /* Enable ProfileMe mode. */
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/* The event numbers are chosen so we can use them directly if
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PCTR1 is enabled. */
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if (ctr[1].enabled) {
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ctl |= (ctr[1].event & 3) << 2;
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} else {
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if (ctr[0].event == 0) /* cycles */
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ctl |= 1UL << 2;
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}
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reg->mux_select = ctl;
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/* Select logging options. */
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/* ??? Need to come up with some mechanism to trace only
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selected processes. EV67 does not have a mechanism to
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select kernel or user mode only. For now, enable always. */
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reg->proc_mode = 0;
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/* EV67 cannot change the width of the counters as with the
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other implementations. But fortunately, we can write to
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the counters and set the value such that it will overflow
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at the right time. */
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reset = need_reset = 0;
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for (i = 0; i < 2; ++i) {
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unsigned long count = ctr[i].count;
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if (!ctr[i].enabled)
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continue;
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if (count > 0x100000)
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count = 0x100000;
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ctr[i].count = count;
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reset |= (0x100000 - count) << (i ? 6 : 28);
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if (count != 0x100000)
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need_reset |= 1 << i;
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}
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reg->reset_values = reset;
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reg->need_reset = need_reset;
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}
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/* Program all of the registers in preparation for enabling profiling. */
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static void
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ev67_cpu_setup (void *x)
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{
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struct op_register_config *reg = x;
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wrperfmon(2, reg->mux_select);
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wrperfmon(3, reg->proc_mode);
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wrperfmon(6, reg->reset_values | 3);
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}
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/* CTR is a counter for which the user has requested an interrupt count
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in between one of the widths selectable in hardware. Reset the count
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for CTR to the value stored in REG->RESET_VALUES. */
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static void
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ev67_reset_ctr(struct op_register_config *reg, unsigned long ctr)
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{
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wrperfmon(6, reg->reset_values | (1 << ctr));
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}
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/* ProfileMe conditions which will show up as counters. We can also
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detect the following, but it seems unlikely that anybody is
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interested in counting them:
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* Reset
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* MT_FPCR (write to floating point control register)
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* Arithmetic trap
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* Dstream Fault
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* Machine Check (ECC fault, etc.)
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* OPCDEC (illegal opcode)
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* Floating point disabled
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* Differentiate between DTB single/double misses and 3 or 4 level
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page tables
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* Istream access violation
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* Interrupt
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* Icache Parity Error.
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* Instruction killed (nop, trapb)
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Unfortunately, there seems to be no way to detect Dcache and Bcache
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misses; the latter could be approximated by making the counter
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count Bcache misses, but that is not precise.
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We model this as 20 counters:
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* PCTR0
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* PCTR1
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* 9 ProfileMe events, induced by PCTR0
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* 9 ProfileMe events, induced by PCTR1
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*/
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enum profileme_counters {
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PM_STALLED, /* Stalled for at least one cycle
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between the fetch and map stages */
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PM_TAKEN, /* Conditional branch taken */
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PM_MISPREDICT, /* Branch caused mispredict trap */
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PM_ITB_MISS, /* ITB miss */
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PM_DTB_MISS, /* DTB miss */
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PM_REPLAY, /* Replay trap */
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PM_LOAD_STORE, /* Load-store order trap */
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PM_ICACHE_MISS, /* Icache miss */
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PM_UNALIGNED, /* Unaligned Load/Store */
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PM_NUM_COUNTERS
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};
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static inline void
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op_add_pm(unsigned long pc, int kern, unsigned long counter,
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struct op_counter_config *ctr, unsigned long event)
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{
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unsigned long fake_counter = 2 + event;
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if (counter == 1)
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fake_counter += PM_NUM_COUNTERS;
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if (ctr[fake_counter].enabled)
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oprofile_add_pc(pc, kern, fake_counter);
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}
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static void
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ev67_handle_interrupt(unsigned long which, struct pt_regs *regs,
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struct op_counter_config *ctr)
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{
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unsigned long pmpc, pctr_ctl;
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int kern = !user_mode(regs);
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int mispredict = 0;
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union {
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unsigned long v;
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struct {
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unsigned reserved: 30; /* 0-29 */
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unsigned overcount: 3; /* 30-32 */
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unsigned icache_miss: 1; /* 33 */
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unsigned trap_type: 4; /* 34-37 */
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unsigned load_store: 1; /* 38 */
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unsigned trap: 1; /* 39 */
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unsigned mispredict: 1; /* 40 */
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} fields;
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} i_stat;
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enum trap_types {
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TRAP_REPLAY,
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TRAP_INVALID0,
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TRAP_DTB_DOUBLE_MISS_3,
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TRAP_DTB_DOUBLE_MISS_4,
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TRAP_FP_DISABLED,
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TRAP_UNALIGNED,
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TRAP_DTB_SINGLE_MISS,
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TRAP_DSTREAM_FAULT,
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TRAP_OPCDEC,
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TRAP_INVALID1,
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TRAP_MACHINE_CHECK,
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TRAP_INVALID2,
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TRAP_ARITHMETIC,
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TRAP_INVALID3,
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TRAP_MT_FPCR,
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TRAP_RESET
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};
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pmpc = wrperfmon(9, 0);
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/* ??? Don't know how to handle physical-mode PALcode address. */
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if (pmpc & 1)
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return;
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pmpc &= ~2; /* clear reserved bit */
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i_stat.v = wrperfmon(8, 0);
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if (i_stat.fields.trap) {
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switch (i_stat.fields.trap_type) {
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case TRAP_INVALID1:
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case TRAP_INVALID2:
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case TRAP_INVALID3:
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/* Pipeline redirection ocurred. PMPC points
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to PALcode. Recognize ITB miss by PALcode
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offset address, and get actual PC from
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EXC_ADDR. */
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oprofile_add_pc(regs->pc, kern, which);
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if ((pmpc & ((1 << 15) - 1)) == 581)
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op_add_pm(regs->pc, kern, which,
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ctr, PM_ITB_MISS);
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/* Most other bit and counter values will be
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those for the first instruction in the
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fault handler, so we're done. */
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return;
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case TRAP_REPLAY:
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op_add_pm(pmpc, kern, which, ctr,
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(i_stat.fields.load_store
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? PM_LOAD_STORE : PM_REPLAY));
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break;
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case TRAP_DTB_DOUBLE_MISS_3:
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case TRAP_DTB_DOUBLE_MISS_4:
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case TRAP_DTB_SINGLE_MISS:
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op_add_pm(pmpc, kern, which, ctr, PM_DTB_MISS);
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break;
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case TRAP_UNALIGNED:
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op_add_pm(pmpc, kern, which, ctr, PM_UNALIGNED);
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break;
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case TRAP_INVALID0:
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case TRAP_FP_DISABLED:
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case TRAP_DSTREAM_FAULT:
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case TRAP_OPCDEC:
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case TRAP_MACHINE_CHECK:
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case TRAP_ARITHMETIC:
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case TRAP_MT_FPCR:
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case TRAP_RESET:
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break;
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}
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/* ??? JSR/JMP/RET/COR or HW_JSR/HW_JMP/HW_RET/HW_COR
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mispredicts do not set this bit but can be
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recognized by the presence of one of these
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instructions at the PMPC location with bit 39
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set. */
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if (i_stat.fields.mispredict) {
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mispredict = 1;
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op_add_pm(pmpc, kern, which, ctr, PM_MISPREDICT);
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}
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}
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oprofile_add_pc(pmpc, kern, which);
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pctr_ctl = wrperfmon(5, 0);
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if (pctr_ctl & (1UL << 27))
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op_add_pm(pmpc, kern, which, ctr, PM_STALLED);
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/* Unfortunately, TAK is undefined on mispredicted branches.
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??? It is also undefined for non-cbranch insns, should
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check that. */
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if (!mispredict && pctr_ctl & (1UL << 0))
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op_add_pm(pmpc, kern, which, ctr, PM_TAKEN);
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}
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struct op_axp_model op_model_ev67 = {
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.reg_setup = ev67_reg_setup,
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.cpu_setup = ev67_cpu_setup,
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.reset_ctr = ev67_reset_ctr,
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.handle_interrupt = ev67_handle_interrupt,
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.cpu_type = "alpha/ev67",
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.num_counters = 20,
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.can_set_proc_mode = 0,
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};
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