388b78adc9
1. Add an option to include RapidIO support if the PCI is available. 2. Add FSL_RIO configuration option to enable controller selection. 3. Add RapidIO support option into x86 and MIPS architectures. Signed-off-by: Alexandre Bounine <alexandre.bounine@idt.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Cc: Matt Porter <mporter@kernel.crashing.org> Cc: Li Yang <leoli@freescale.com> Cc: Thomas Moll <thomas.moll@sysgo.com> Cc: Micha Nelissen <micha@neli.hopto.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
96 lines
2.1 KiB
ArmAsm
96 lines
2.1 KiB
ArmAsm
/*
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* This file contains low level CPU setup functions.
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* Kumar Gala <galak@kernel.crashing.org>
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* Based on cpu_setup_6xx code by
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/processor.h>
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#include <asm/cputable.h>
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#include <asm/ppc_asm.h>
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_GLOBAL(__e500_icache_setup)
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mfspr r0, SPRN_L1CSR1
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andi. r3, r0, L1CSR1_ICE
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bnelr /* Already enabled */
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oris r0, r0, L1CSR1_CPE@h
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ori r0, r0, (L1CSR1_ICFI | L1CSR1_ICLFR | L1CSR1_ICE)
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mtspr SPRN_L1CSR1, r0 /* Enable I-Cache */
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isync
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blr
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_GLOBAL(__e500_dcache_setup)
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mfspr r0, SPRN_L1CSR0
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andi. r3, r0, L1CSR0_DCE
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bnelr /* Already enabled */
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msync
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isync
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li r0, 0
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mtspr SPRN_L1CSR0, r0 /* Disable */
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msync
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isync
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li r0, (L1CSR0_DCFI | L1CSR0_CLFC)
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mtspr SPRN_L1CSR0, r0 /* Invalidate */
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isync
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1: mfspr r0, SPRN_L1CSR0
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andi. r3, r0, L1CSR0_CLFC
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bne+ 1b /* Wait for lock bits reset */
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oris r0, r0, L1CSR0_CPE@h
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ori r0, r0, L1CSR0_DCE
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msync
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isync
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mtspr SPRN_L1CSR0, r0 /* Enable */
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isync
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blr
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#ifdef CONFIG_PPC32
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_GLOBAL(__setup_cpu_e200)
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/* enable dedicated debug exception handling resources (Debug APU) */
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mfspr r3,SPRN_HID0
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ori r3,r3,HID0_DAPUEN@l
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mtspr SPRN_HID0,r3
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b __setup_e200_ivors
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_GLOBAL(__setup_cpu_e500v1)
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_GLOBAL(__setup_cpu_e500v2)
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mflr r4
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bl __e500_icache_setup
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bl __e500_dcache_setup
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bl __setup_e500_ivors
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#ifdef CONFIG_FSL_RIO
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/* Ensure that RFXE is set */
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mfspr r3,SPRN_HID1
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oris r3,r3,HID1_RFXE@h
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mtspr SPRN_HID1,r3
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#endif
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mtlr r4
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blr
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_GLOBAL(__setup_cpu_e500mc)
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mflr r4
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bl __e500_icache_setup
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bl __e500_dcache_setup
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bl __setup_e500mc_ivors
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mtlr r4
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blr
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#endif
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/* Right now, restore and setup are the same thing */
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_GLOBAL(__restore_cpu_e5500)
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_GLOBAL(__setup_cpu_e5500)
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mflr r4
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bl __e500_icache_setup
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bl __e500_dcache_setup
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#ifdef CONFIG_PPC_BOOK3E_64
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bl .__setup_base_ivors
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#else
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bl __setup_e500mc_ivors
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#endif
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mtlr r4
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blr
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