56344d822e
Sorry, no sekr1t mips c0dez ;-) Signed-off-by: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
108 lines
3.6 KiB
C
108 lines
3.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __MIPSNET_H
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#define __MIPSNET_H
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/*
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* Id of this Net device, as seen by the core.
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*/
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#define MIPS_NET_DEV_ID ((uint64_t) \
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((uint64_t)'M'<< 0)| \
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((uint64_t)'I'<< 8)| \
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((uint64_t)'P'<<16)| \
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((uint64_t)'S'<<24)| \
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((uint64_t)'N'<<32)| \
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((uint64_t)'E'<<40)| \
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((uint64_t)'T'<<48)| \
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((uint64_t)'0'<<56))
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/*
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* Net status/control block as seen by sw in the core.
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* (Why not use bit fields? can't be bothered with cross-platform struct
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* packing.)
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*/
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typedef struct _net_control_block {
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/// dev info for probing
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/// reads as MIPSNET%d where %d is some form of version
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uint64_t devId; /*0x00 */
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/*
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* read only busy flag.
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* Set and cleared by the Net Device to indicate that an rx or a tx
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* is in progress.
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*/
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uint32_t busy; /*0x08 */
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/*
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* Set by the Net Device.
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* The device will set it once data has been received.
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* The value is the number of bytes that should be read from
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* rxDataBuffer. The value will decrease till 0 until all the data
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* from rxDataBuffer has been read.
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*/
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uint32_t rxDataCount; /*0x0c */
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#define MIPSNET_MAX_RXTX_DATACOUNT (1<<16)
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/*
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* Settable from the MIPS core, cleared by the Net Device.
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* The core should set the number of bytes it wants to send,
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* then it should write those bytes of data to txDataBuffer.
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* The device will clear txDataCount has been processed (not necessarily sent).
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*/
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uint32_t txDataCount; /*0x10 */
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/*
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* Interrupt control
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*
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* Used to clear the interrupted generated by this dev.
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* Write a 1 to clear the interrupt. (except bit31).
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*
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* Bit0 is set if it was a tx-done interrupt.
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* Bit1 is set when new rx-data is available.
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* Until this bit is cleared there will be no other RXs.
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*
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* Bit31 is used for testing, it clears after a read.
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* Writing 1 to this bit will cause an interrupt to be generated.
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* To clear the test interrupt, write 0 to this register.
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*/
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uint32_t interruptControl; /*0x14 */
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#define MIPSNET_INTCTL_TXDONE ((uint32_t)(1<< 0))
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#define MIPSNET_INTCTL_RXDONE ((uint32_t)(1<< 1))
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#define MIPSNET_INTCTL_TESTBIT ((uint32_t)(1<<31))
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#define MIPSNET_INTCTL_ALLSOURCES (MIPSNET_INTCTL_TXDONE|MIPSNET_INTCTL_RXDONE|MIPSNET_INTCTL_TESTBIT)
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/*
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* Readonly core-specific interrupt info for the device to signal the core.
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* The meaning of the contents of this field might change.
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*/
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/*###\todo: the whole memIntf interrupt scheme is messy: the device should have
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* no control what so ever of what VPE/register set is being used.
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* The MemIntf should only expose interrupt lines, and something in the
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* config should be responsible for the line<->core/vpe bindings.
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*/
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uint32_t interruptInfo; /*0x18 */
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/*
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* This is where the received data is read out.
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* There is more data to read until rxDataReady is 0.
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* Only 1 byte at this regs offset is used.
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*/
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uint32_t rxDataBuffer; /*0x1c */
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/*
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* This is where the data to transmit is written.
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* Data should be written for the amount specified in the txDataCount register.
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* Only 1 byte at this regs offset is used.
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*/
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uint32_t txDataBuffer; /*0x20 */
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} MIPS_T_NetControl;
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#define MIPSNET_IO_EXTENT 0x40 /* being generous */
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#define field_offset(field) ((int)&((MIPS_T_NetControl*)(0))->field)
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#endif /* __MIPSNET_H */
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