b9dbf95177
The STI hardware is based on a single 48-bit 32kHz counter that together with two individual compare registers can generate interrupts. There are no timer operating modes selectable which means that the timer can not clear on match. This driver is providing clocksource support for the 48-bit counter. Clockevents are also supported using the same timer in oneshot mode. Signed-off-by: Magnus Damm <damm@opensource.se> Cc: horms@verge.net.au Cc: arnd@arndb.de Cc: johnstul@us.ibm.com Cc: rjw@sisk.pl Cc: lethal@linux-sh.org Cc: gregkh@linuxfoundation.org Cc: olof@lixom.net Link: http://lkml.kernel.org/r/20120525070344.23443.69756.sendpatchset@w520 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
13 lines
570 B
Makefile
13 lines
570 B
Makefile
obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
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obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
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obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
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obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
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obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
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obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o
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obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
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obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
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obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
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obj-$(CONFIG_CLKBLD_I8253) += i8253.o
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obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
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obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
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obj-$(CONFIG_CLKSRC_DBX500_PRCMU) += clksrc-dbx500-prcmu.o
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