333b08ee8c
This patch 1. Add support for device-tree binding for ECAP APWM driver. 2. Set size of pwm-cells set to 3 to support PWM channel number, PWM period & polarity configuration from device tree. 3. Add enable/disable clock gating in PWM subsystem common config space. 4. When here set .owner member in platform_driver structure to THIS_MODULE. Signed-off-by: Philip, Avinash <avinashphilip@ti.com> Cc: Grant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Rob Landley <rob@landley.net> Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
300 lines
7.6 KiB
C
300 lines
7.6 KiB
C
/*
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* ECAP PWM driver
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*
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* Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/pm_runtime.h>
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#include <linux/pwm.h>
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#include <linux/of_device.h>
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#include "pwm-tipwmss.h"
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/* ECAP registers and bits definitions */
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#define CAP1 0x08
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#define CAP2 0x0C
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#define CAP3 0x10
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#define CAP4 0x14
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#define ECCTL2 0x2A
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#define ECCTL2_APWM_POL_LOW BIT(10)
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#define ECCTL2_APWM_MODE BIT(9)
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#define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
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#define ECCTL2_TSCTR_FREERUN BIT(4)
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struct ecap_pwm_chip {
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struct pwm_chip chip;
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unsigned int clk_rate;
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void __iomem *mmio_base;
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};
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static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
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{
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return container_of(chip, struct ecap_pwm_chip, chip);
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}
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/*
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* period_ns = 10^9 * period_cycles / PWM_CLK_RATE
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* duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
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*/
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static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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int duty_ns, int period_ns)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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unsigned long long c;
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unsigned long period_cycles, duty_cycles;
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unsigned int reg_val;
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if (period_ns > NSEC_PER_SEC)
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return -ERANGE;
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c = pc->clk_rate;
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c = c * period_ns;
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do_div(c, NSEC_PER_SEC);
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period_cycles = (unsigned long)c;
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if (period_cycles < 1) {
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period_cycles = 1;
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duty_cycles = 1;
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} else {
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c = pc->clk_rate;
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c = c * duty_ns;
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do_div(c, NSEC_PER_SEC);
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duty_cycles = (unsigned long)c;
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}
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pm_runtime_get_sync(pc->chip.dev);
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reg_val = readw(pc->mmio_base + ECCTL2);
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/* Configure APWM mode & disable sync option */
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reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
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writew(reg_val, pc->mmio_base + ECCTL2);
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if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
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/* Update active registers if not running */
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writel(duty_cycles, pc->mmio_base + CAP2);
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writel(period_cycles, pc->mmio_base + CAP1);
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} else {
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/*
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* Update shadow registers to configure period and
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* compare values. This helps current PWM period to
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* complete on reconfiguring
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*/
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writel(duty_cycles, pc->mmio_base + CAP4);
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writel(period_cycles, pc->mmio_base + CAP3);
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}
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if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
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reg_val = readw(pc->mmio_base + ECCTL2);
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/* Disable APWM mode to put APWM output Low */
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reg_val &= ~ECCTL2_APWM_MODE;
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writew(reg_val, pc->mmio_base + ECCTL2);
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}
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pm_runtime_put_sync(pc->chip.dev);
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return 0;
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}
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static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
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enum pwm_polarity polarity)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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unsigned short reg_val;
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pm_runtime_get_sync(pc->chip.dev);
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reg_val = readw(pc->mmio_base + ECCTL2);
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if (polarity == PWM_POLARITY_INVERSED)
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/* Duty cycle defines LOW period of PWM */
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reg_val |= ECCTL2_APWM_POL_LOW;
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else
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/* Duty cycle defines HIGH period of PWM */
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reg_val &= ~ECCTL2_APWM_POL_LOW;
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writew(reg_val, pc->mmio_base + ECCTL2);
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pm_runtime_put_sync(pc->chip.dev);
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return 0;
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}
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static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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unsigned int reg_val;
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/* Leave clock enabled on enabling PWM */
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pm_runtime_get_sync(pc->chip.dev);
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/*
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* Enable 'Free run Time stamp counter mode' to start counter
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* and 'APWM mode' to enable APWM output
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*/
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reg_val = readw(pc->mmio_base + ECCTL2);
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reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
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writew(reg_val, pc->mmio_base + ECCTL2);
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return 0;
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}
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static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
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unsigned int reg_val;
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/*
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* Disable 'Free run Time stamp counter mode' to stop counter
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* and 'APWM mode' to put APWM output to low
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*/
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reg_val = readw(pc->mmio_base + ECCTL2);
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reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
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writew(reg_val, pc->mmio_base + ECCTL2);
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/* Disable clock on PWM disable */
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pm_runtime_put_sync(pc->chip.dev);
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}
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static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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{
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if (test_bit(PWMF_ENABLED, &pwm->flags)) {
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dev_warn(chip->dev, "Removing PWM device without disabling\n");
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pm_runtime_put_sync(chip->dev);
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}
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}
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static const struct pwm_ops ecap_pwm_ops = {
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.free = ecap_pwm_free,
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.config = ecap_pwm_config,
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.set_polarity = ecap_pwm_set_polarity,
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.enable = ecap_pwm_enable,
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.disable = ecap_pwm_disable,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id ecap_of_match[] = {
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{ .compatible = "ti,am33xx-ecap" },
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{},
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};
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MODULE_DEVICE_TABLE(of, ecap_of_match);
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static int __devinit ecap_pwm_probe(struct platform_device *pdev)
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{
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int ret;
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struct resource *r;
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struct clk *clk;
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struct ecap_pwm_chip *pc;
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u16 status;
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pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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if (!pc) {
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dev_err(&pdev->dev, "failed to allocate memory\n");
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return -ENOMEM;
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}
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clk = devm_clk_get(&pdev->dev, "fck");
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if (IS_ERR(clk)) {
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dev_err(&pdev->dev, "failed to get clock\n");
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return PTR_ERR(clk);
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}
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pc->clk_rate = clk_get_rate(clk);
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if (!pc->clk_rate) {
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dev_err(&pdev->dev, "failed to get clock rate\n");
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return -EINVAL;
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}
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pc->chip.dev = &pdev->dev;
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pc->chip.ops = &ecap_pwm_ops;
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pc->chip.of_xlate = of_pwm_xlate_with_flags;
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pc->chip.of_pwm_n_cells = 3;
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pc->chip.base = -1;
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pc->chip.npwm = 1;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "no memory resource defined\n");
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return -ENODEV;
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}
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pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
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if (!pc->mmio_base)
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return -EADDRNOTAVAIL;
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ret = pwmchip_add(&pc->chip);
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if (ret < 0) {
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dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
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return ret;
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}
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pm_runtime_enable(&pdev->dev);
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pm_runtime_get_sync(&pdev->dev);
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status = pwmss_submodule_state_change(pdev->dev.parent,
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PWMSS_ECAPCLK_EN);
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if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
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dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
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ret = -EINVAL;
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goto pwmss_clk_failure;
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}
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pm_runtime_put_sync(&pdev->dev);
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platform_set_drvdata(pdev, pc);
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return 0;
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pwmss_clk_failure:
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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pwmchip_remove(&pc->chip);
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return ret;
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}
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static int __devexit ecap_pwm_remove(struct platform_device *pdev)
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{
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struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
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pm_runtime_get_sync(&pdev->dev);
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/*
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* Due to hardware misbehaviour, acknowledge of the stop_req
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* is missing. Hence checking of the status bit skipped.
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*/
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pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_put_sync(&pdev->dev);
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pm_runtime_disable(&pdev->dev);
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return pwmchip_remove(&pc->chip);
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}
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static struct platform_driver ecap_pwm_driver = {
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.driver = {
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.name = "ecap",
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.owner = THIS_MODULE,
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.of_match_table = ecap_of_match,
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},
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.probe = ecap_pwm_probe,
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.remove = __devexit_p(ecap_pwm_remove),
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};
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module_platform_driver(ecap_pwm_driver);
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MODULE_DESCRIPTION("ECAP PWM driver");
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MODULE_AUTHOR("Texas Instruments");
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MODULE_LICENSE("GPL");
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