David Daney 325f8a0a31 MIPS: Two-level pagetables for 64-bit kernels with 64KB pages. ... For 64-bit kernels with 64KB pages and two level page tables, there are 42 bits worth of virtual address space This is larger than the 40 bits of virtual address space obtained with the default 4KB Page size and three levels, so there are no draw backs for using two level tables with this configuration. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/761/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2010-02-27 12:53:03 +01:00
..
c-octeon.c	MIPS: Fix __devinit __cpuinit confusion in cpu_cache_init	2010-02-10 22:15:45 +01:00
c-r3k.c
c-r4k.c
c-tx39.c
cache.c	MIPS: Fix __devinit __cpuinit confusion in cpu_cache_init	2010-02-10 22:15:45 +01:00
cerr-sb1.c	MIPS: Sibyte: Use hweight8 instead of counting bits	2009-12-17 01:57:16 +00:00
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c	MIPS: Add DMA declare coherent memory support	2009-11-13 18:10:37 +01:00
extable.c
fault.c	MIPS: Don't corrupt page tables on vmalloc fault.	2009-09-17 20:07:52 +02:00
highmem.c	MIPS: Highmem: Fix build error	2010-02-22 21:42:11 +01:00
hugetlbpage.c
init.c	MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.	2010-02-27 12:53:03 +01:00
ioremap.c
Makefile
page.c
pgtable-32.c
pgtable-64.c	MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.	2010-02-27 12:53:03 +01:00
sc-ip22.c
sc-mips.c	MIPS: MIPSxx SC: Avoid destructive invalidation on partial L2 cachelines.	2009-09-30 21:47:00 +02:00
sc-r5k.c
sc-rm7k.c
tlb-r3k.c
tlb-r4k.c	MIPS: Remove useless zero initializations.	2009-09-17 20:07:51 +02:00
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: Two-level pagetables for 64-bit kernels with 64KB pages.	2010-02-27 12:53:03 +01:00
uasm.c	MIPS: Add drotr and dins instructions to uasm.	2009-12-17 01:57:01 +00:00
uasm.h	MIPS: Add drotr and dins instructions to uasm.	2009-12-17 01:57:01 +00:00