32351a28a7
This adds preliminary support for the SH7785-based Highlander board. Some of the Highlander support code is reordered so that most of it can be reused directly. This also plugs in missing SH7785 checks in the places that need it, as this is the first board to support the CPU. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
96 lines
3.6 KiB
C
96 lines
3.6 KiB
C
/*
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* Low-Level PCI Support for SH7780 targets
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*
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* Dustin McIntire (dustin@sensoria.com) (c) 2001
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* Paul Mundt (lethal@linux-sh.org) (c) 2003
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*
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*/
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#ifndef _PCI_SH7780_H_
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#define _PCI_SH7780_H_
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/* Platform Specific Values */
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#define SH7780_VENDOR_ID 0x1912
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#define SH7781_DEVICE_ID 0x0001
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#define SH7780_DEVICE_ID 0x0002
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#define SH7785_DEVICE_ID 0x0007
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/* SH7780 Control Registers */
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#define SH7780_PCI_VCR0 0xFE000000
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#define SH7780_PCI_VCR1 0xFE000004
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#define SH7780_PCI_VCR2 0xFE000008
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/* SH7780 Specific Values */
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#define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */
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#define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */
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#define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */
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#define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
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#define SH7780_PCI_IO_BASE 0xFE400000 /* IO space base address */
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#define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */
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#define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */
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#define PCI_REG(n) (SH7780_PCIREG_BASE+n)
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/* SH7780 PCI Config Registers */
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#define SH7780_PCIVID 0x000 /* Vendor ID */
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#define SH7780_PCIDID 0x002 /* Device ID */
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#define SH7780_PCICMD 0x004 /* Command */
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#define SH7780_PCISTATUS 0x006 /* Status */
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#define SH7780_PCIRID 0x008 /* Revision ID */
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#define SH7780_PCIPIF 0x009 /* Program Interface */
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#define SH7780_PCISUB 0x00a /* Sub class code */
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#define SH7780_PCIBCC 0x00b /* Base class code */
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#define SH7780_PCICLS 0x00c /* Cache line size */
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#define SH7780_PCILTM 0x00d /* latency timer */
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#define SH7780_PCIHDR 0x00e /* Header type */
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#define SH7780_PCIBIST 0x00f /* BIST */
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#define SH7780_PCIIBAR 0x010 /* IO Base address */
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#define SH7780_PCIMBAR0 0x014 /* Memory base address0 */
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#define SH7780_PCIMBAR1 0x018 /* Memory base address1 */
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#define SH7780_PCISVID 0x02c /* Sub system vendor ID */
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#define SH7780_PCISID 0x02e /* Sub system ID */
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#define SH7780_PCICP 0x034
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#define SH7780_PCIINTLINE 0x03c /* Interrupt line */
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#define SH7780_PCIINTPIN 0x03d /* Interrupt pin */
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#define SH7780_PCIMINGNT 0x03e /* Minumum grand */
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#define SH7780_PCIMAXLAT 0x03f /* Maxmum latency */
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#define SH7780_PCICID 0x040
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#define SH7780_PCINIP 0x041
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#define SH7780_PCIPMC 0x042
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#define SH7780_PCIPMCSR 0x044
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#define SH7780_PCIPMCSR_BSE 0x046
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#define SH7780_PCICDD 0x047
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#define SH7780_PCIMBR0 0x1E0
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#define SH7780_PCIMBMR0 0x1E4
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#define SH7780_PCIMBR2 0x1F0
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#define SH7780_PCIMBMR2 0x1F4
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#define SH7780_PCIIOBR 0x1F8
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#define SH7780_PCIIOBMR 0x1FC
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#define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */
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#define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */
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#define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */
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#define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */
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/* General Memory Config Addresses */
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#define SH7780_CS0_BASE_ADDR 0x0
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#define SH7780_MEM_REGION_SIZE 0x04000000
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#define SH7780_CS1_BASE_ADDR (SH7780_CS0_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS2_BASE_ADDR (SH7780_CS1_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS3_BASE_ADDR (SH7780_CS2_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS4_BASE_ADDR (SH7780_CS3_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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#define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE)
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struct sh4_pci_address_map;
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/* arch/sh/drivers/pci/pci-sh7780.c */
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int sh7780_pcic_init(struct sh4_pci_address_map *map);
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#endif /* _PCI_SH7780_H_ */
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