1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
407 lines
11 KiB
C
407 lines
11 KiB
C
/*
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* drivers/mtd/nand/tx4938ndfmc.c
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*
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* Overview:
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* This is a device driver for the NAND flash device connected to
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* TX4938 internal NAND Memory Controller.
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* TX4938 NDFMC is almost same as TX4925 NDFMC, but register size are 64 bit.
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*
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* Author: source@mvista.com
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*
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* Based on spia.c by Steven J. Hill
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*
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* $Id: tx4938ndfmc.c,v 1.4 2004/10/05 13:50:20 gleixner Exp $
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/config.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <asm/io.h>
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#include <asm/bootinfo.h>
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#include <linux/delay.h>
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#include <asm/tx4938/rbtx4938.h>
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extern struct nand_oobinfo jffs2_oobinfo;
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/*
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* MTD structure for TX4938 NDFMC
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*/
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static struct mtd_info *tx4938ndfmc_mtd;
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/*
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* Define partitions for flash device
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*/
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#define flush_wb() (void)tx4938_ndfmcptr->mcr;
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#define NUM_PARTITIONS 3
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#define NUMBER_OF_CIS_BLOCKS 24
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#define SIZE_OF_BLOCK 0x00004000
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#define NUMBER_OF_BLOCK_PER_ZONE 1024
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#define SIZE_OF_ZONE (NUMBER_OF_BLOCK_PER_ZONE * SIZE_OF_BLOCK)
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#ifndef CONFIG_MTD_CMDLINE_PARTS
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/*
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* You can use the following sample of MTD partitions
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* on the NAND Flash Memory 32MB or more.
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*
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* The following figure shows the image of the sample partition on
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* the 32MB NAND Flash Memory.
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*
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* Block No.
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* 0 +-----------------------------+ ------
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* | CIS | ^
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* 24 +-----------------------------+ |
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* | kernel image | | Zone 0
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* | | |
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* +-----------------------------+ |
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* 1023 | unused area | v
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* +-----------------------------+ ------
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* 1024 | JFFS2 | ^
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* | | |
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* | | | Zone 1
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* | | |
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* | | |
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* | | v
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* 2047 +-----------------------------+ ------
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*
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*/
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static struct mtd_partition partition_info[NUM_PARTITIONS] = {
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{
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.name = "RBTX4938 CIS Area",
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.offset = 0,
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.size = (NUMBER_OF_CIS_BLOCKS * SIZE_OF_BLOCK),
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.mask_flags = MTD_WRITEABLE /* This partition is NOT writable */
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},
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{
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.name = "RBTX4938 kernel image",
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.offset = MTDPART_OFS_APPEND,
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.size = 8 * 0x00100000, /* 8MB (Depends on size of kernel image) */
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.mask_flags = MTD_WRITEABLE /* This partition is NOT writable */
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},
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{
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.name = "Root FS (JFFS2)",
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.offset = (0 + SIZE_OF_ZONE), /* start address of next zone */
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.size = MTDPART_SIZ_FULL
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},
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};
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#endif
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static void tx4938ndfmc_hwcontrol(struct mtd_info *mtd, int cmd)
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{
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switch (cmd) {
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case NAND_CTL_SETCLE:
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tx4938_ndfmcptr->mcr |= TX4938_NDFMCR_CLE;
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break;
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case NAND_CTL_CLRCLE:
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tx4938_ndfmcptr->mcr &= ~TX4938_NDFMCR_CLE;
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break;
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case NAND_CTL_SETALE:
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tx4938_ndfmcptr->mcr |= TX4938_NDFMCR_ALE;
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break;
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case NAND_CTL_CLRALE:
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tx4938_ndfmcptr->mcr &= ~TX4938_NDFMCR_ALE;
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break;
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/* TX4938_NDFMCR_CE bit is 0:high 1:low */
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case NAND_CTL_SETNCE:
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tx4938_ndfmcptr->mcr |= TX4938_NDFMCR_CE;
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break;
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case NAND_CTL_CLRNCE:
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tx4938_ndfmcptr->mcr &= ~TX4938_NDFMCR_CE;
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break;
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case NAND_CTL_SETWP:
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tx4938_ndfmcptr->mcr |= TX4938_NDFMCR_WE;
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break;
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case NAND_CTL_CLRWP:
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tx4938_ndfmcptr->mcr &= ~TX4938_NDFMCR_WE;
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break;
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}
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}
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static int tx4938ndfmc_dev_ready(struct mtd_info *mtd)
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{
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flush_wb();
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return !(tx4938_ndfmcptr->sr & TX4938_NDFSR_BUSY);
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}
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static void tx4938ndfmc_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
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{
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u32 mcr = tx4938_ndfmcptr->mcr;
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mcr &= ~TX4938_NDFMCR_ECC_ALL;
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tx4938_ndfmcptr->mcr = mcr | TX4938_NDFMCR_ECC_OFF;
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tx4938_ndfmcptr->mcr = mcr | TX4938_NDFMCR_ECC_READ;
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ecc_code[1] = tx4938_ndfmcptr->dtr;
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ecc_code[0] = tx4938_ndfmcptr->dtr;
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ecc_code[2] = tx4938_ndfmcptr->dtr;
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tx4938_ndfmcptr->mcr = mcr | TX4938_NDFMCR_ECC_OFF;
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}
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static void tx4938ndfmc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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u32 mcr = tx4938_ndfmcptr->mcr;
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mcr &= ~TX4938_NDFMCR_ECC_ALL;
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tx4938_ndfmcptr->mcr = mcr | TX4938_NDFMCR_ECC_RESET;
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tx4938_ndfmcptr->mcr = mcr | TX4938_NDFMCR_ECC_OFF;
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tx4938_ndfmcptr->mcr = mcr | TX4938_NDFMCR_ECC_ON;
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}
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static u_char tx4938ndfmc_nand_read_byte(struct mtd_info *mtd)
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{
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struct nand_chip *this = mtd->priv;
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return tx4938_read_nfmc(this->IO_ADDR_R);
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}
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static void tx4938ndfmc_nand_write_byte(struct mtd_info *mtd, u_char byte)
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{
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struct nand_chip *this = mtd->priv;
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tx4938_write_nfmc(byte, this->IO_ADDR_W);
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}
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static void tx4938ndfmc_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++)
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tx4938_write_nfmc(buf[i], this->IO_ADDR_W);
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}
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static void tx4938ndfmc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++)
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buf[i] = tx4938_read_nfmc(this->IO_ADDR_R);
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}
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static int tx4938ndfmc_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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struct nand_chip *this = mtd->priv;
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for (i=0; i<len; i++)
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if (buf[i] != tx4938_read_nfmc(this->IO_ADDR_R))
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return -EFAULT;
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return 0;
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}
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/*
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* Send command to NAND device
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*/
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static void tx4938ndfmc_nand_command (struct mtd_info *mtd, unsigned command, int column, int page_addr)
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{
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register struct nand_chip *this = mtd->priv;
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/* Begin command latch cycle */
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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/*
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* Write out the command to the device.
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*/
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if (command == NAND_CMD_SEQIN) {
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int readcmd;
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if (column >= mtd->oobblock) {
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/* OOB area */
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column -= mtd->oobblock;
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readcmd = NAND_CMD_READOOB;
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} else if (column < 256) {
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/* First 256 bytes --> READ0 */
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readcmd = NAND_CMD_READ0;
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} else {
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column -= 256;
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readcmd = NAND_CMD_READ1;
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}
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this->write_byte(mtd, readcmd);
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}
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this->write_byte(mtd, command);
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/* Set ALE and clear CLE to start address cycle */
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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if (column != -1 || page_addr != -1) {
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this->hwcontrol(mtd, NAND_CTL_SETALE);
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/* Serially input address */
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if (column != -1)
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this->write_byte(mtd, column);
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if (page_addr != -1) {
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this->write_byte(mtd, (unsigned char) (page_addr & 0xff));
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this->write_byte(mtd, (unsigned char) ((page_addr >> 8) & 0xff));
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/* One more address cycle for higher density devices */
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if (mtd->size & 0x0c000000)
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this->write_byte(mtd, (unsigned char) ((page_addr >> 16) & 0x0f));
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}
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/* Latch in address */
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this->hwcontrol(mtd, NAND_CTL_CLRALE);
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}
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/*
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* program and erase have their own busy handlers
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* status and sequential in needs no delay
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*/
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switch (command) {
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case NAND_CMD_PAGEPROG:
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/* Turn off WE */
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this->hwcontrol (mtd, NAND_CTL_CLRWP);
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return;
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case NAND_CMD_SEQIN:
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/* Turn on WE */
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this->hwcontrol (mtd, NAND_CTL_SETWP);
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return;
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case NAND_CMD_ERASE1:
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case NAND_CMD_ERASE2:
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case NAND_CMD_STATUS:
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return;
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case NAND_CMD_RESET:
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if (this->dev_ready)
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break;
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this->hwcontrol(mtd, NAND_CTL_SETCLE);
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this->write_byte(mtd, NAND_CMD_STATUS);
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this->hwcontrol(mtd, NAND_CTL_CLRCLE);
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while ( !(this->read_byte(mtd) & 0x40));
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return;
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/* This applies to read commands */
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default:
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/*
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* If we don't have access to the busy pin, we apply the given
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* command delay
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*/
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if (!this->dev_ready) {
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udelay (this->chip_delay);
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return;
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}
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}
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/* wait until command is processed */
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while (!this->dev_ready(mtd));
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}
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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extern int parse_cmdline_partitions(struct mtd_info *master, struct mtd_partition **pparts, char *);
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#endif
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/*
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* Main initialization routine
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*/
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int __init tx4938ndfmc_init (void)
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{
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struct nand_chip *this;
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int bsprt = 0, hold = 0xf, spw = 0xf;
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int protected = 0;
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if ((*rbtx4938_piosel_ptr & 0x0c) != 0x08) {
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printk("TX4938 NDFMC: disabled by IOC PIOSEL\n");
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return -ENODEV;
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}
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bsprt = 1;
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hold = 2;
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spw = 9 - 1; /* 8 GBUSCLK = 80ns (@ GBUSCLK 100MHz) */
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if ((tx4938_ccfgptr->pcfg &
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(TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL))
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!= TX4938_PCFG_NDF_SEL) {
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printk("TX4938 NDFMC: disabled by PCFG.\n");
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return -ENODEV;
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}
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/* reset NDFMC */
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tx4938_ndfmcptr->rstr |= TX4938_NDFRSTR_RST;
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while (tx4938_ndfmcptr->rstr & TX4938_NDFRSTR_RST)
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;
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/* setup BusSeparete, Hold Time, Strobe Pulse Width */
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tx4938_ndfmcptr->mcr = bsprt ? TX4938_NDFMCR_BSPRT : 0;
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tx4938_ndfmcptr->spr = hold << 4 | spw;
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/* Allocate memory for MTD device structure and private data */
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tx4938ndfmc_mtd = kmalloc (sizeof(struct mtd_info) + sizeof (struct nand_chip),
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GFP_KERNEL);
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if (!tx4938ndfmc_mtd) {
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printk ("Unable to allocate TX4938 NDFMC MTD device structure.\n");
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return -ENOMEM;
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}
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/* Get pointer to private data */
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this = (struct nand_chip *) (&tx4938ndfmc_mtd[1]);
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/* Initialize structures */
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memset((char *) tx4938ndfmc_mtd, 0, sizeof(struct mtd_info));
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memset((char *) this, 0, sizeof(struct nand_chip));
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/* Link the private data with the MTD structure */
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tx4938ndfmc_mtd->priv = this;
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/* Set address of NAND IO lines */
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this->IO_ADDR_R = (unsigned long)&tx4938_ndfmcptr->dtr;
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this->IO_ADDR_W = (unsigned long)&tx4938_ndfmcptr->dtr;
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this->hwcontrol = tx4938ndfmc_hwcontrol;
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this->dev_ready = tx4938ndfmc_dev_ready;
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this->calculate_ecc = tx4938ndfmc_calculate_ecc;
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this->correct_data = nand_correct_data;
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this->enable_hwecc = tx4938ndfmc_enable_hwecc;
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this->eccmode = NAND_ECC_HW3_256;
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this->chip_delay = 100;
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this->read_byte = tx4938ndfmc_nand_read_byte;
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this->write_byte = tx4938ndfmc_nand_write_byte;
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this->cmdfunc = tx4938ndfmc_nand_command;
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this->write_buf = tx4938ndfmc_nand_write_buf;
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this->read_buf = tx4938ndfmc_nand_read_buf;
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this->verify_buf = tx4938ndfmc_nand_verify_buf;
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/* Scan to find existance of the device */
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if (nand_scan (tx4938ndfmc_mtd, 1)) {
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kfree (tx4938ndfmc_mtd);
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return -ENXIO;
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}
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if (protected) {
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printk(KERN_INFO "TX4938 NDFMC: write protected.\n");
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tx4938ndfmc_mtd->flags &= ~(MTD_WRITEABLE | MTD_ERASEABLE);
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}
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#ifdef CONFIG_MTD_CMDLINE_PARTS
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{
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int mtd_parts_nb = 0;
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struct mtd_partition *mtd_parts = 0;
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mtd_parts_nb = parse_cmdline_partitions(tx4938ndfmc_mtd, &mtd_parts, "tx4938ndfmc");
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if (mtd_parts_nb > 0)
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add_mtd_partitions(tx4938ndfmc_mtd, mtd_parts, mtd_parts_nb);
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else
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add_mtd_device(tx4938ndfmc_mtd);
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}
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#else
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add_mtd_partitions(tx4938ndfmc_mtd, partition_info, NUM_PARTITIONS );
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#endif
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return 0;
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}
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module_init(tx4938ndfmc_init);
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/*
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* Clean up routine
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*/
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static void __exit tx4938ndfmc_cleanup (void)
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{
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/* Release resources, unregister device */
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nand_release (tx4938ndfmc_mtd);
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/* Free the MTD device structure */
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kfree (tx4938ndfmc_mtd);
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}
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module_exit(tx4938ndfmc_cleanup);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Alice Hennessy <ahennessy@mvista.com>");
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MODULE_DESCRIPTION("Board-specific glue layer for NAND flash on TX4938 NDFMC");
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