1855a2c4ce
When we bring up a new CPU via INIT/startup IPI messages, the CPU that's coming up sends a xTPR message to the chipset. Intel chipsets (at least) don't provide any architectural guarantee on what the chipset will do with this message. For example, the E850x chipsets uses this xTPR message to interpret the interrupt operating mode of the platform. When the CPU coming online sends this message, it always indicates that it is in logical flat mode. For the CPU hotplug case, the platform may already be functioning in cluster APIC mode at this time, the chipset can get confused and mishandle I/O device and IPI interrupt routing. The situation eventually gets corrected when the new CPU sends another xTPR update when we switch it to cluster mode, but there's a window during which the chipset may be in an inconsistent state. This patch avoids this problem by using the flat physical interrupt delivery mode instead of cluster mode for bigsmp (>8 cpu) support. Signed-off-by: Ashok Raj <ashok.raj@intel.com> Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
14 lines
227 B
C
14 lines
227 B
C
#ifndef __ASM_MACH_APICDEF_H
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#define __ASM_MACH_APICDEF_H
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#define APIC_ID_MASK (0xFF<<24)
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static inline unsigned get_apic_id(unsigned long x)
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{
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return (((x)>>24)&0xFF);
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}
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#define GET_APIC_ID(x) get_apic_id(x)
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#endif
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