173 lines
4.3 KiB
C
173 lines
4.3 KiB
C
/*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/page.h>
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#include <linux/io.h>
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#include <asm/prom.h>
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#include <asm/irq.h>
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#ifdef CONFIG_SELFMOD_INTC
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#include <asm/selfmod.h>
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#define INTC_BASE BARRIER_BASE_ADDR
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#else
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static unsigned int intc_baseaddr;
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#define INTC_BASE intc_baseaddr
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#endif
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unsigned int nr_irq;
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/* No one else should require these constants, so define them locally here. */
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#define ISR 0x00 /* Interrupt Status Register */
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#define IPR 0x04 /* Interrupt Pending Register */
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#define IER 0x08 /* Interrupt Enable Register */
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#define IAR 0x0c /* Interrupt Acknowledge Register */
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#define SIE 0x10 /* Set Interrupt Enable bits */
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#define CIE 0x14 /* Clear Interrupt Enable bits */
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#define IVR 0x18 /* Interrupt Vector Register */
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#define MER 0x1c /* Master Enable Register */
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#define MER_ME (1<<0)
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#define MER_HIE (1<<1)
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static void intc_enable_or_unmask(unsigned int irq)
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{
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pr_debug("enable_or_unmask: %d\n", irq);
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out_be32(INTC_BASE + SIE, 1 << irq);
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}
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static void intc_disable_or_mask(unsigned int irq)
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{
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pr_debug("disable: %d\n", irq);
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out_be32(INTC_BASE + CIE, 1 << irq);
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}
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static void intc_ack(unsigned int irq)
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{
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pr_debug("ack: %d\n", irq);
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out_be32(INTC_BASE + IAR, 1 << irq);
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}
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static void intc_mask_ack(unsigned int irq)
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{
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unsigned long mask = 1 << irq;
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pr_debug("disable_and_ack: %d\n", irq);
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out_be32(INTC_BASE + CIE, mask);
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out_be32(INTC_BASE + IAR, mask);
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}
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static void intc_end(unsigned int irq)
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{
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unsigned long mask = 1 << irq;
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pr_debug("end: %d\n", irq);
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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out_be32(INTC_BASE + SIE, mask);
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/* ack level sensitive intr */
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if (irq_desc[irq].status & IRQ_LEVEL)
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out_be32(INTC_BASE + IAR, mask);
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}
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}
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static struct irq_chip intc_dev = {
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.name = "Xilinx INTC",
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.unmask = intc_enable_or_unmask,
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.mask = intc_disable_or_mask,
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.ack = intc_ack,
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.mask_ack = intc_mask_ack,
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.end = intc_end,
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};
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unsigned int get_irq(struct pt_regs *regs)
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{
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int irq;
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/*
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* NOTE: This function is the one that needs to be improved in
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* order to handle multiple interrupt controllers. It currently
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* is hardcoded to check for interrupts only on the first INTC.
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*/
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irq = in_be32(INTC_BASE + IVR);
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pr_debug("get_irq: %d\n", irq);
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return irq;
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}
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void __init init_IRQ(void)
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{
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u32 i, j, intr_type;
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struct device_node *intc = NULL;
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#ifdef CONFIG_SELFMOD_INTC
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unsigned int intc_baseaddr = 0;
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static int arr_func[] = {
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(int)&get_irq,
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(int)&intc_enable_or_unmask,
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(int)&intc_disable_or_mask,
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(int)&intc_mask_ack,
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(int)&intc_ack,
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(int)&intc_end,
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0
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};
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#endif
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static char *intc_list[] = {
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"xlnx,xps-intc-1.00.a",
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"xlnx,opb-intc-1.00.c",
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"xlnx,opb-intc-1.00.b",
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"xlnx,opb-intc-1.00.a",
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NULL
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};
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for (j = 0; intc_list[j] != NULL; j++) {
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intc = of_find_compatible_node(NULL, NULL, intc_list[j]);
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if (intc)
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break;
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}
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intc_baseaddr = *(int *) of_get_property(intc, "reg", NULL);
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intc_baseaddr = (unsigned long) ioremap(intc_baseaddr, PAGE_SIZE);
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nr_irq = *(int *) of_get_property(intc, "xlnx,num-intr-inputs", NULL);
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intr_type =
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*(int *) of_get_property(intc, "xlnx,kind-of-intr", NULL);
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if (intr_type >= (1 << (nr_irq + 1)))
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printk(KERN_INFO " ERROR: Mismatch in kind-of-intr param\n");
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#ifdef CONFIG_SELFMOD_INTC
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selfmod_function((int *) arr_func, intc_baseaddr);
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#endif
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printk(KERN_INFO "%s #0 at 0x%08x, num_irq=%d, edge=0x%x\n",
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intc_list[j], intc_baseaddr, nr_irq, intr_type);
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/*
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* Disable all external interrupts until they are
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* explicity requested.
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*/
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out_be32(intc_baseaddr + IER, 0);
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/* Acknowledge any pending interrupts just in case. */
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out_be32(intc_baseaddr + IAR, 0xffffffff);
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/* Turn on the Master Enable. */
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out_be32(intc_baseaddr + MER, MER_HIE | MER_ME);
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for (i = 0; i < nr_irq; ++i) {
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if (intr_type & (0x00000001 << i)) {
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set_irq_chip_and_handler_name(i, &intc_dev,
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handle_edge_irq, intc_dev.name);
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irq_desc[i].status &= ~IRQ_LEVEL;
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} else {
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set_irq_chip_and_handler_name(i, &intc_dev,
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handle_level_irq, intc_dev.name);
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irq_desc[i].status |= IRQ_LEVEL;
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}
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}
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}
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