01001712c9
This patch updates the common machine specific source files with support for TI816X. Signed-off-by: Hemant Pedanekar <hemantp@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
171 lines
4.3 KiB
ArmAsm
171 lines
4.3 KiB
ArmAsm
/*
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* arch/arm/plat-omap/include/mach/entry-macro.S
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*
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* Low-level IRQ helper macros for OMAP-based platforms
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*
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* Copyright (C) 2009 Texas Instruments
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* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <mach/hardware.h>
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#include <mach/io.h>
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#include <mach/irqs.h>
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#include <asm/hardware/gic.h>
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#include <plat/omap24xx.h>
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#include <plat/omap34xx.h>
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#include <plat/omap44xx.h>
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#include <plat/multi.h>
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#define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
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#define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
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#define OMAP4_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE)
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#define INTCPS_SIR_IRQ_OFFSET 0x0040 /* omap2/3 active interrupt offset */
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#define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */
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.macro disable_fiq
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.endm
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.macro arch_ret_to_user, tmp1, tmp2
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.endm
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/*
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* Unoptimized irq functions for multi-omap2, 3 and 4
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*/
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#ifdef MULTI_OMAP2
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/*
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* Configure the interrupt base on the first interrupt.
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* See also omap_irq_base_init for setting omap_irq_base.
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*/
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =omap_irq_base @ irq base address
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ldr \base, [\base, #0] @ irq base value
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.endm
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/* Check the pending interrupts. Note that base already set */
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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tst \base, #0x100 @ gic address?
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bne 4401f @ found gic
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/* Handle omap2 and omap3 */
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ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
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cmp \irqnr, #0x0
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bne 9998f
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ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
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cmp \irqnr, #0x0
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bne 9998f
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ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
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cmp \irqnr, #0x0
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bne 9998f
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/*
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* ti816x has additional IRQ pending register. Checking this
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* register on omap2 & omap3 has no effect (read as 0).
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*/
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ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
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cmp \irqnr, #0x0
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9998:
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ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
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and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
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b 9999f
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/* Handle omap4 */
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4401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
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ldr \tmp, =1021
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #29
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cmpcc \irqnr, \irqnr
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cmpne \irqnr, \tmp
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cmpcs \irqnr, \irqnr
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9999:
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.endm
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#ifdef CONFIG_SMP
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/* We assume that irqstat (the raw value of the IRQ acknowledge
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* register) is preserved from the macro above.
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* If there is an IPI, we immediately signal end of interrupt
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* on the controller, since this requires the original irqstat
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* value which we won't easily be able to recreate later.
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*/
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.macro test_for_ipi, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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cmp \irqnr, #16
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it cc
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strcc \irqstat, [\base, #GIC_CPU_EOI]
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it cs
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cmpcs \irqnr, \irqnr
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.endm
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/* As above, this assumes that irqstat and base are preserved */
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.macro test_for_ltirq, irqnr, irqstat, base, tmp
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bic \irqnr, \irqstat, #0x1c00
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mov \tmp, #0
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cmp \irqnr, #29
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itt eq
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moveq \tmp, #1
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streq \irqstat, [\base, #GIC_CPU_EOI]
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cmp \tmp, #0
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.endm
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#endif /* CONFIG_SMP */
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#else /* MULTI_OMAP2 */
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/*
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* Optimized irq functions for omap2, 3 and 4
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*/
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#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
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.macro get_irqnr_preamble, base, tmp
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#ifdef CONFIG_ARCH_OMAP2
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ldr \base, =OMAP2_IRQ_BASE
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#else
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ldr \base, =OMAP3_IRQ_BASE
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#endif
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.endm
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/* Check the pending interrupts. Note that base already set */
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
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ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */
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cmp \irqnr, #0x0
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bne 9999f
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ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */
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cmp \irqnr, #0x0
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bne 9999f
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ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */
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cmp \irqnr, #0x0
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#ifdef CONFIG_SOC_OMAPTI816X
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bne 9999f
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ldr \irqnr, [\base, #0xf8] /* IRQ pending reg 4 */
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cmp \irqnr, #0x0
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#endif
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9999:
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ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET]
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and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */
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.endm
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#endif
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#ifdef CONFIG_ARCH_OMAP4
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#define HAVE_GET_IRQNR_PREAMBLE
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#include <asm/hardware/entry-macro-gic.S>
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.macro get_irqnr_preamble, base, tmp
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ldr \base, =OMAP4_IRQ_BASE
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.endm
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#endif
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#endif /* MULTI_OMAP2 */
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.macro irq_prio_table
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.endm
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