1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
401 lines
14 KiB
C
401 lines
14 KiB
C
#ifdef __KERNEL__
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#ifndef _ASM_IRQ_H
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#define _ASM_IRQ_H
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#include <linux/config.h>
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#include <asm/machdep.h> /* ppc_md */
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#include <asm/atomic.h>
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/*
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* These constants are used for passing information about interrupt
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* signal polarity and level/edge sensing to the low-level PIC chip
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* drivers.
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*/
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#define IRQ_SENSE_MASK 0x1
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#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
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#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
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#define IRQ_POLARITY_MASK 0x2
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#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
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#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
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#if defined(CONFIG_40x)
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#include <asm/ibm4xx.h>
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#ifndef NR_BOARD_IRQS
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#define NR_BOARD_IRQS 0
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#endif
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#ifndef UIC_WIDTH /* Number of interrupts per device */
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#define UIC_WIDTH 32
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#endif
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#ifndef NR_UICS /* number of UIC devices */
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#define NR_UICS 1
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#endif
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#if defined (CONFIG_403)
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/*
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* The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
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* 32 possible interrupts, a majority of which are not implemented on
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* all cores. There are six configurable, external interrupt pins and
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* there are eight internal interrupts for the on-chip serial port
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* (SPU), DMA controller, and JTAG controller.
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*
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*/
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#define NR_AIC_IRQS 32
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#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
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#elif !defined (CONFIG_403)
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/*
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* The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
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* possible interrupts as well. There are seven, configurable external
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* interrupt pins and there are 17 internal interrupts for the on-chip
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* serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
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*
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*/
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#define NR_UIC_IRQS UIC_WIDTH
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#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
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#endif
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static __inline__ int
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irq_canonicalize(int irq)
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{
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return (irq);
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}
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#elif defined(CONFIG_44x)
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#include <asm/ibm44x.h>
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#define NR_UIC_IRQS 32
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#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
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static __inline__ int
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irq_canonicalize(int irq)
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{
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return (irq);
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}
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#elif defined(CONFIG_8xx)
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/* Now include the board configuration specific associations.
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*/
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#include <asm/mpc8xx.h>
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/* The MPC8xx cores have 16 possible interrupts. There are eight
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* possible level sensitive interrupts assigned and generated internally
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* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
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* There are eight external interrupts (IRQs) that can be configured
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* as either level or edge sensitive.
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*
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* On some implementations, there is also the possibility of an 8259
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* through the PCI and PCI-ISA bridges.
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*
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* We are "flattening" the interrupt vectors of the cascaded CPM
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* and 8259 interrupt controllers so that we can uniquely identify
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* any interrupt source with a single integer.
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*/
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#define NR_SIU_INTS 16
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#define NR_CPM_INTS 32
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#ifndef NR_8259_INTS
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#define NR_8259_INTS 0
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#endif
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#define SIU_IRQ_OFFSET 0
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#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
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#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
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#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
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/* These values must be zero-based and map 1:1 with the SIU configuration.
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* They are used throughout the 8xx I/O subsystem to generate
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* interrupt masks, flags, and other control patterns. This is why the
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* current kernel assumption of the 8259 as the base controller is such
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* a pain in the butt.
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*/
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#define SIU_IRQ0 (0) /* Highest priority */
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#define SIU_LEVEL0 (1)
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#define SIU_IRQ1 (2)
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#define SIU_LEVEL1 (3)
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#define SIU_IRQ2 (4)
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#define SIU_LEVEL2 (5)
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#define SIU_IRQ3 (6)
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#define SIU_LEVEL3 (7)
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#define SIU_IRQ4 (8)
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#define SIU_LEVEL4 (9)
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#define SIU_IRQ5 (10)
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#define SIU_LEVEL5 (11)
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#define SIU_IRQ6 (12)
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#define SIU_LEVEL6 (13)
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#define SIU_IRQ7 (14)
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#define SIU_LEVEL7 (15)
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/* The internal interrupts we can configure as we see fit.
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* My personal preference is CPM at level 2, which puts it above the
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* MBX PCI/ISA/IDE interrupts.
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*/
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#ifndef PIT_INTERRUPT
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#define PIT_INTERRUPT SIU_LEVEL0
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#endif
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#ifndef CPM_INTERRUPT
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#define CPM_INTERRUPT SIU_LEVEL2
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#endif
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#ifndef PCMCIA_INTERRUPT
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#define PCMCIA_INTERRUPT SIU_LEVEL6
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#endif
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#ifndef DEC_INTERRUPT
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#define DEC_INTERRUPT SIU_LEVEL7
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#endif
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/* Some internal interrupt registers use an 8-bit mask for the interrupt
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* level instead of a number.
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*/
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#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
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/* always the same on 8xx -- Cort */
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static __inline__ int irq_canonicalize(int irq)
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{
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return irq;
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}
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#elif defined(CONFIG_83xx)
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#include <asm/mpc83xx.h>
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static __inline__ int irq_canonicalize(int irq)
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{
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return irq;
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}
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#define NR_IRQS (NR_IPIC_INTS)
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#elif defined(CONFIG_85xx)
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/* Now include the board configuration specific associations.
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*/
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#include <asm/mpc85xx.h>
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/* The MPC8560 openpic has 32 internal interrupts and 12 external
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* interrupts.
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*
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* We are "flattening" the interrupt vectors of the cascaded CPM
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* so that we can uniquely identify any interrupt source with a
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* single integer.
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*/
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#define NR_CPM_INTS 64
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#define NR_EPIC_INTS 44
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#ifndef NR_8259_INTS
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#define NR_8259_INTS 0
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#endif
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#define NUM_8259_INTERRUPTS NR_8259_INTS
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#ifndef CPM_IRQ_OFFSET
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#define CPM_IRQ_OFFSET 0
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#endif
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#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
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/* Internal IRQs on MPC85xx OpenPIC */
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#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
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#ifdef CONFIG_CPM2
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#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
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#else
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#define MPC85xx_OPENPIC_IRQ_OFFSET 0
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#endif
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#endif
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/* Not all of these exist on all MPC85xx implementations */
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#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
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/* The 12 external interrupt lines */
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#define MPC85xx_IRQ_EXT0 (32 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT1 (33 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT2 (34 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT3 (35 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT4 (36 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT5 (37 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT6 (38 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT7 (39 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT8 (40 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT9 (41 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT10 (42 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT11 (43 + MPC85xx_OPENPIC_IRQ_OFFSET)
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/* CPM related interrupts */
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#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
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#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
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#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
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#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
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#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
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#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
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#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
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#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
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#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
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#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
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#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
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#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
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#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
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#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
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#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
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#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
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#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
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#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
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#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
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#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
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#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
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#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
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#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
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#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
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#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
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#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
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#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
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#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
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#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
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#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
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#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
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#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
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static __inline__ int irq_canonicalize(int irq)
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{
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return irq;
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}
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#else /* CONFIG_40x + CONFIG_8xx */
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/*
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* this is the # irq's for all ppc arch's (pmac/chrp/prep)
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* so it is the max of them all
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*/
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#define NR_IRQS 256
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#ifndef CONFIG_8260
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#define NUM_8259_INTERRUPTS 16
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#else /* CONFIG_8260 */
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/* The 8260 has an internal interrupt controller with a maximum of
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* 64 IRQs. We will use NR_IRQs from above since it is large enough.
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* Don't be confused by the 8260 documentation where they list an
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* "interrupt number" and "interrupt vector". We are only interested
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* in the interrupt vector. There are "reserved" holes where the
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* vector number increases, but the interrupt number in the table does not.
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* (Document errata updates have fixed this...make sure you have up to
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* date processor documentation -- Dan).
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*/
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#ifndef CPM_IRQ_OFFSET
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#define CPM_IRQ_OFFSET 0
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#endif
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#define NR_CPM_INTS 64
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#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
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#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
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#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
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#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
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#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
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#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
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#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
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#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
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#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
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#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
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#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
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#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
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#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
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#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
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#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
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#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
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#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
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#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
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#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
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#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
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#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
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#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
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#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
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#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
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#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
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#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
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#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
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#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
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#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
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#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
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#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
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#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
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#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
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#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
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#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
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#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
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#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
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#endif /* CONFIG_8260 */
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/*
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* This gets called from serial.c, which is now used on
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* powermacs as well as prep/chrp boxes.
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* Prep and chrp both have cascaded 8259 PICs.
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*/
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static __inline__ int irq_canonicalize(int irq)
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{
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if (ppc_md.irq_canonicalize)
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return ppc_md.irq_canonicalize(irq);
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return irq;
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}
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|
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#endif
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|
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|
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
|
|
/* pedantic: these are long because they are used with set_bit --RR */
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|
extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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|
extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
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|
extern atomic_t ppc_n_lost_interrupts;
|
|
|
|
struct irqaction;
|
|
struct pt_regs;
|
|
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
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|
|
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#endif /* _ASM_IRQ_H */
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|
#endif /* __KERNEL__ */
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