d4d8fbcef0
Convert AMD (Xilinx) sd-fec bindings to yaml format, so it can validate dt-entries as well as any future additions to yaml. Change in clocks is due to IP is itself configurable and only the first two clocks are in all combinations. The last 6 clocks can be present in some of them. It means order is not really fixed and any combination is possible. Interrupt may or may not be present. The documentation for sd-fec bindings is now YAML, so update the MAINTAINERS file. Update the link to the new yaml file in xilinx_sdfec.rst. Signed-off-by: Dragan Cvetic <dragan.cvetic@amd.com> Link: https://lore.kernel.org/r/20240131170650.530079-1-dragan.cvetic@amd.com Signed-off-by: Rob Herring <robh@kernel.org> |
||
|---|---|---|
| .. | ||
| ad525x_dpot.rst | ||
| apds990x.rst | ||
| bh1770glc.rst | ||
| c2port.rst | ||
| dw-xdata-pcie.rst | ||
| ibmvmc.rst | ||
| ics932s401.rst | ||
| index.rst | ||
| isl29003.rst | ||
| lis3lv02d.rst | ||
| max6875.rst | ||
| oxsemi-tornado.rst | ||
| pci-endpoint-test.rst | ||
| spear-pcie-gadget.rst | ||
| tps6594-pfsm.rst | ||
| uacce.rst | ||
| xilinx_sdfec.rst | ||