59b6978745
This patch introduces a new function that checks the running status of a cpu in a hypervisor. This status is not virtualized, so the check is only correct if running in an LPAR. On acquiring a spinlock, if the cpu holding the lock is scheduled by the hypervisor, we do a busy wait on the lock. If it is not scheduled, we yield over to that cpu. Signed-off-by: Gerald Schaefer <gerald.schaefer@de.ibm.com> Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
132 lines
2.5 KiB
C
132 lines
2.5 KiB
C
/*
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* Routines and structures for signalling other processors.
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*
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* Copyright IBM Corp. 1999,2010
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* Author(s): Denis Joseph Barrow,
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* Martin Schwidefsky <schwidefsky@de.ibm.com>,
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* Heiko Carstens <heiko.carstens@de.ibm.com>,
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*/
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#ifndef __ASM_SIGP_H
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#define __ASM_SIGP_H
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#include <asm/system.h>
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/* Get real cpu address from logical cpu number. */
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extern unsigned short __cpu_logical_map[];
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static inline int cpu_logical_map(int cpu)
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{
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#ifdef CONFIG_SMP
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return __cpu_logical_map[cpu];
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#else
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return stap();
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#endif
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}
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enum {
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sigp_sense = 1,
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sigp_external_call = 2,
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sigp_emergency_signal = 3,
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sigp_start = 4,
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sigp_stop = 5,
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sigp_restart = 6,
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sigp_stop_and_store_status = 9,
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sigp_initial_cpu_reset = 11,
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sigp_cpu_reset = 12,
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sigp_set_prefix = 13,
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sigp_store_status_at_address = 14,
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sigp_store_extended_status_at_address = 15,
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sigp_set_architecture = 18,
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sigp_conditional_emergency_signal = 19,
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sigp_sense_running = 21,
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};
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enum {
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sigp_order_code_accepted = 0,
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sigp_status_stored = 1,
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sigp_busy = 2,
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sigp_not_operational = 3,
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};
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/*
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* Definitions for external call.
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*/
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enum {
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ec_schedule = 0,
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ec_call_function,
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ec_call_function_single,
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};
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/*
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* Signal processor.
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*/
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static inline int raw_sigp(u16 cpu, int order)
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{
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register unsigned long reg1 asm ("1") = 0;
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int ccode;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (ccode)
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: "d" (reg1), "d" (cpu),
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"a" (order) : "cc" , "memory");
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return ccode;
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}
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/*
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* Signal processor with parameter.
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*/
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static inline int raw_sigp_p(u32 parameter, u16 cpu, int order)
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{
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register unsigned int reg1 asm ("1") = parameter;
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int ccode;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (ccode)
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: "d" (reg1), "d" (cpu),
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"a" (order) : "cc" , "memory");
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return ccode;
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}
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/*
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* Signal processor with parameter and return status.
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*/
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static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order)
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{
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register unsigned int reg1 asm ("1") = parm;
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int ccode;
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asm volatile(
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" sigp %1,%2,0(%3)\n"
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" ipm %0\n"
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" srl %0,28\n"
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: "=d" (ccode), "+d" (reg1)
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: "d" (cpu), "a" (order)
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: "cc" , "memory");
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*status = reg1;
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return ccode;
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}
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static inline int sigp(int cpu, int order)
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{
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return raw_sigp(cpu_logical_map(cpu), order);
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}
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static inline int sigp_p(u32 parameter, int cpu, int order)
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{
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return raw_sigp_p(parameter, cpu_logical_map(cpu), order);
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}
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static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order)
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{
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return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order);
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}
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#endif /* __ASM_SIGP_H */
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