cf1c5fae5f
Calculate PLL configuration based on input data: sensor configuration, board properties and sensor-specific limits. [mchehab@redhat.com: Fix a Kconfig conflict affecting APTINA_PLL] Signed-off-by: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
104 lines
2.7 KiB
C
104 lines
2.7 KiB
C
/*
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* drivers/media/video/smiapp-pll.h
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*
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* Generic driver for SMIA/SMIA++ compliant camera modules
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*
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* Copyright (C) 2012 Nokia Corporation
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* Contact: Sakari Ailus <sakari.ailus@maxwell.research.nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef SMIAPP_PLL_H
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#define SMIAPP_PLL_H
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#include <linux/device.h>
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struct smiapp_pll {
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uint8_t lanes;
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uint8_t binning_horizontal;
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uint8_t binning_vertical;
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uint8_t scale_m;
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uint8_t scale_n;
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uint8_t bits_per_pixel;
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uint16_t flags;
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uint32_t link_freq;
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uint16_t pre_pll_clk_div;
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uint16_t pll_multiplier;
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uint16_t op_sys_clk_div;
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uint16_t op_pix_clk_div;
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uint16_t vt_sys_clk_div;
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uint16_t vt_pix_clk_div;
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uint32_t ext_clk_freq_hz;
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uint32_t pll_ip_clk_freq_hz;
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uint32_t pll_op_clk_freq_hz;
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uint32_t op_sys_clk_freq_hz;
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uint32_t op_pix_clk_freq_hz;
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uint32_t vt_sys_clk_freq_hz;
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uint32_t vt_pix_clk_freq_hz;
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uint32_t pixel_rate_csi;
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};
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struct smiapp_pll_limits {
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/* Strict PLL limits */
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uint32_t min_ext_clk_freq_hz;
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uint32_t max_ext_clk_freq_hz;
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uint16_t min_pre_pll_clk_div;
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uint16_t max_pre_pll_clk_div;
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uint32_t min_pll_ip_freq_hz;
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uint32_t max_pll_ip_freq_hz;
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uint16_t min_pll_multiplier;
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uint16_t max_pll_multiplier;
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uint32_t min_pll_op_freq_hz;
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uint32_t max_pll_op_freq_hz;
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uint16_t min_vt_sys_clk_div;
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uint16_t max_vt_sys_clk_div;
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uint32_t min_vt_sys_clk_freq_hz;
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uint32_t max_vt_sys_clk_freq_hz;
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uint16_t min_vt_pix_clk_div;
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uint16_t max_vt_pix_clk_div;
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uint32_t min_vt_pix_clk_freq_hz;
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uint32_t max_vt_pix_clk_freq_hz;
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uint16_t min_op_sys_clk_div;
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uint16_t max_op_sys_clk_div;
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uint32_t min_op_sys_clk_freq_hz;
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uint32_t max_op_sys_clk_freq_hz;
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uint16_t min_op_pix_clk_div;
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uint16_t max_op_pix_clk_div;
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uint32_t min_op_pix_clk_freq_hz;
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uint32_t max_op_pix_clk_freq_hz;
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/* Other relevant limits */
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uint32_t min_line_length_pck_bin;
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uint32_t min_line_length_pck;
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};
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/* op pix clock is for all lanes in total normally */
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#define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0)
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#define SMIAPP_PLL_FLAG_NO_OP_CLOCKS (1 << 1)
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struct device;
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int smiapp_pll_calculate(struct device *dev, struct smiapp_pll_limits *limits,
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struct smiapp_pll *pll);
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#endif /* SMIAPP_PLL_H */
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