d96a980441
All current Simtec designs source the DCLK outputs from the UPLL. This means the DCLK's parent must be set to UPLL so that anything enabling and disabling an UPLL sourced clock does not shutdown the DCLK due to missing open counts. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
464 lines
10 KiB
C
464 lines
10 KiB
C
/* linux/arch/arm/mach-s3c2440/mach-anubis.c
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*
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* Copyright (c) 2003-2005 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/timer.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/platform_device.h>
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#include <linux/sm501.h>
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#include <linux/sm501-regs.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/irq.h>
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#include <asm/arch/anubis-map.h>
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#include <asm/arch/anubis-irq.h>
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#include <asm/arch/anubis-cpld.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach-types.h>
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#include <asm/plat-s3c/regs-serial.h>
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#include <asm/arch/regs-gpio.h>
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#include <asm/arch/regs-mem.h>
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#include <asm/arch/regs-lcd.h>
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#include <asm/plat-s3c/nand.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/nand_ecc.h>
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#include <linux/mtd/partitions.h>
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#include <net/ax88796.h>
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#include <asm/plat-s3c24xx/clock.h>
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#include <asm/plat-s3c24xx/devs.h>
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#include <asm/plat-s3c24xx/cpu.h>
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#define COPYRIGHT ", (c) 2005 Simtec Electronics"
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static struct map_desc anubis_iodesc[] __initdata = {
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/* ISA IO areas */
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{
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.virtual = (u32)S3C24XX_VA_ISA_BYTE,
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.pfn = __phys_to_pfn(0x0),
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.length = SZ_4M,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)S3C24XX_VA_ISA_WORD,
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.pfn = __phys_to_pfn(0x0),
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.length = SZ_4M,
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.type = MT_DEVICE,
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},
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/* we could possibly compress the next set down into a set of smaller tables
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* pagetables, but that would mean using an L2 section, and it still means
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* we cannot actually feed the same register to an LDR due to 16K spacing
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*/
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/* CPLD control registers */
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{
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.virtual = (u32)ANUBIS_VA_CTRL1,
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.pfn = __phys_to_pfn(ANUBIS_PA_CTRL1),
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.length = SZ_4K,
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.type = MT_DEVICE,
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}, {
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.virtual = (u32)ANUBIS_VA_IDREG,
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.pfn = __phys_to_pfn(ANUBIS_PA_IDREG),
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.length = SZ_4K,
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.type = MT_DEVICE,
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},
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};
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#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
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#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
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#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
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static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
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[0] = {
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.name = "uclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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},
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[1] = {
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.name = "pclk",
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.divisor = 1,
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.min_baud = 0,
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.max_baud = 0,
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}
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};
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static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
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[0] = {
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.hwport = 0,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clocks = anubis_serial_clocks,
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.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
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},
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[1] = {
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.hwport = 2,
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.flags = 0,
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.ucon = UCON,
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.ulcon = ULCON,
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.ufcon = UFCON,
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.clocks = anubis_serial_clocks,
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.clocks_size = ARRAY_SIZE(anubis_serial_clocks),
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},
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};
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/* NAND Flash on Anubis board */
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static int external_map[] = { 2 };
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static int chip0_map[] = { 0 };
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static int chip1_map[] = { 1 };
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static struct mtd_partition anubis_default_nand_part[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_16K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_16K,
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.offset = SZ_16K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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static struct mtd_partition anubis_default_nand_part_large[] = {
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[0] = {
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.name = "Boot Agent",
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.size = SZ_128K,
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.offset = 0,
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},
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[1] = {
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.name = "/boot",
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.size = SZ_4M - SZ_128K,
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.offset = SZ_128K,
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},
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[2] = {
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.name = "user1",
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.offset = SZ_4M,
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.size = SZ_32M - SZ_4M,
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},
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[3] = {
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.name = "user2",
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.offset = SZ_32M,
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.size = MTDPART_SIZ_FULL,
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}
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};
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/* the Anubis has 3 selectable slots for nand-flash, the two
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* on-board chip areas, as well as the external slot.
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*
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* Note, there is no current hot-plug support for the External
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* socket.
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*/
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static struct s3c2410_nand_set anubis_nand_sets[] = {
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[1] = {
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.name = "External",
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.nr_chips = 1,
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.nr_map = external_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part,
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},
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[0] = {
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.name = "chip0",
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.nr_chips = 1,
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.nr_map = chip0_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part,
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},
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[2] = {
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.name = "chip1",
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.nr_chips = 1,
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.nr_map = chip1_map,
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.nr_partitions = ARRAY_SIZE(anubis_default_nand_part),
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.partitions = anubis_default_nand_part,
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},
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};
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static void anubis_nand_select(struct s3c2410_nand_set *set, int slot)
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{
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unsigned int tmp;
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slot = set->nr_map[slot] & 3;
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pr_debug("anubis_nand: selecting slot %d (set %p,%p)\n",
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slot, set, set->nr_map);
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tmp = __raw_readb(ANUBIS_VA_CTRL1);
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tmp &= ~ANUBIS_CTRL1_NANDSEL;
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tmp |= slot;
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pr_debug("anubis_nand: ctrl1 now %02x\n", tmp);
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__raw_writeb(tmp, ANUBIS_VA_CTRL1);
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}
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static struct s3c2410_platform_nand anubis_nand_info = {
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.tacls = 25,
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.twrph0 = 55,
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.twrph1 = 40,
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.nr_sets = ARRAY_SIZE(anubis_nand_sets),
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.sets = anubis_nand_sets,
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.select_chip = anubis_nand_select,
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};
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/* IDE channels */
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static struct resource anubis_ide0_resource[] = {
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{
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.start = S3C2410_CS3,
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.end = S3C2410_CS3 + (8*32) - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = S3C2410_CS3 + (1<<26),
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.end = S3C2410_CS3 + (1<<26) + (8*32) - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_IDE0,
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.end = IRQ_IDE0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device anubis_device_ide0 = {
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.name = "simtec-ide",
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.id = 0,
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.num_resources = ARRAY_SIZE(anubis_ide0_resource),
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.resource = anubis_ide0_resource,
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};
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static struct resource anubis_ide1_resource[] = {
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{
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.start = S3C2410_CS4,
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.end = S3C2410_CS4 + (8*32) - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = S3C2410_CS4 + (1<<26),
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.end = S3C2410_CS4 + (1<<26) + (8*32) - 1,
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.flags = IORESOURCE_MEM,
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}, {
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.start = IRQ_IDE0,
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.end = IRQ_IDE0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device anubis_device_ide1 = {
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.name = "simtec-ide",
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.id = 1,
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.num_resources = ARRAY_SIZE(anubis_ide1_resource),
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.resource = anubis_ide1_resource,
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};
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/* Asix AX88796 10/100 ethernet controller */
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static struct ax_plat_data anubis_asix_platdata = {
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.flags = AXFLG_MAC_FROMDEV,
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.wordlength = 2,
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.dcr_val = 0x48,
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.rcr_val = 0x40,
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};
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static struct resource anubis_asix_resource[] = {
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[0] = {
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.start = S3C2410_CS5,
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.end = S3C2410_CS5 + (0x20 * 0x20) -1,
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.flags = IORESOURCE_MEM
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},
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[1] = {
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.start = IRQ_ASIX,
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.end = IRQ_ASIX,
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.flags = IORESOURCE_IRQ
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}
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};
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static struct platform_device anubis_device_asix = {
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.name = "ax88796",
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.id = 0,
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.num_resources = ARRAY_SIZE(anubis_asix_resource),
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.resource = anubis_asix_resource,
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.dev = {
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.platform_data = &anubis_asix_platdata,
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}
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};
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/* SM501 */
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static struct resource anubis_sm501_resource[] = {
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[0] = {
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.start = S3C2410_CS2,
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.end = S3C2410_CS2 + SZ_8M,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = S3C2410_CS2 + SZ_64M - SZ_2M,
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.end = S3C2410_CS2 + SZ_64M - 1,
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.flags = IORESOURCE_MEM,
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},
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[2] = {
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.start = IRQ_EINT0,
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.end = IRQ_EINT0,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct sm501_initdata anubis_sm501_initdata = {
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.gpio_high = {
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.set = 0x3F000000, /* 24bit panel */
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.mask = 0x0,
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},
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.misc_timing = {
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.set = 0x010100, /* SDRAM timing */
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.mask = 0x1F1F00,
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},
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.misc_control = {
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.set = SM501_MISC_PNL_24BIT,
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.mask = 0,
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},
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/* set the SDRAM and bus clocks */
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.mclk = 72 * MHZ,
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.m1xclk = 144 * MHZ,
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};
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static struct sm501_platdata_gpio_i2c anubis_sm501_gpio_i2c[] = {
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[0] = {
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.pin_scl = 44,
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.pin_sda = 45,
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},
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[1] = {
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.pin_scl = 40,
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.pin_sda = 41,
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},
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};
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static struct sm501_platdata anubis_sm501_platdata = {
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.init = &anubis_sm501_initdata,
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.gpio_i2c = anubis_sm501_gpio_i2c,
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.gpio_i2c_nr = ARRAY_SIZE(anubis_sm501_gpio_i2c),
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};
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static struct platform_device anubis_device_sm501 = {
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.name = "sm501",
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.id = 0,
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.num_resources = ARRAY_SIZE(anubis_sm501_resource),
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.resource = anubis_sm501_resource,
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.dev = {
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.platform_data = &anubis_sm501_platdata,
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},
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};
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/* Standard Anubis devices */
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static struct platform_device *anubis_devices[] __initdata = {
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&s3c_device_usb,
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&s3c_device_wdt,
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&s3c_device_adc,
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&s3c_device_i2c,
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&s3c_device_rtc,
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&s3c_device_nand,
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&anubis_device_ide0,
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&anubis_device_ide1,
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&anubis_device_asix,
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&anubis_device_sm501,
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};
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static struct clk *anubis_clocks[] = {
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&s3c24xx_dclk0,
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&s3c24xx_dclk1,
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&s3c24xx_clkout0,
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&s3c24xx_clkout1,
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&s3c24xx_uclk,
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};
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static void __init anubis_map_io(void)
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{
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/* initialise the clocks */
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s3c24xx_dclk0.parent = &clk_upll;
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s3c24xx_dclk0.rate = 12*1000*1000;
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s3c24xx_dclk1.parent = &clk_upll;
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s3c24xx_dclk1.rate = 24*1000*1000;
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s3c24xx_clkout0.parent = &s3c24xx_dclk0;
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s3c24xx_clkout1.parent = &s3c24xx_dclk1;
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s3c24xx_uclk.parent = &s3c24xx_clkout1;
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s3c24xx_register_clocks(anubis_clocks, ARRAY_SIZE(anubis_clocks));
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s3c_device_nand.dev.platform_data = &anubis_nand_info;
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s3c24xx_init_io(anubis_iodesc, ARRAY_SIZE(anubis_iodesc));
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s3c24xx_init_clocks(0);
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s3c24xx_init_uarts(anubis_uartcfgs, ARRAY_SIZE(anubis_uartcfgs));
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/* check for the newer revision boards with large page nand */
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if ((__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK) >= 4) {
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printk(KERN_INFO "ANUBIS-B detected (revision %d)\n",
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__raw_readb(ANUBIS_VA_IDREG) & ANUBIS_IDREG_REVMASK);
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anubis_nand_sets[0].partitions = anubis_default_nand_part_large;
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anubis_nand_sets[0].nr_partitions = ARRAY_SIZE(anubis_default_nand_part_large);
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} else {
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/* ensure that the GPIO is setup */
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s3c2410_gpio_setpin(S3C2410_GPA0, 1);
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}
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}
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static void __init anubis_init(void)
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{
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platform_add_devices(anubis_devices, ARRAY_SIZE(anubis_devices));
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}
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MACHINE_START(ANUBIS, "Simtec-Anubis")
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/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
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.phys_io = S3C2410_PA_UART,
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.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
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.boot_params = S3C2410_SDRAM_PA + 0x100,
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.map_io = anubis_map_io,
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.init_machine = anubis_init,
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.init_irq = s3c24xx_init_irq,
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.timer = &s3c24xx_timer,
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MACHINE_END
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