93173ce272
This patch creates a common system reset routine for all 40x and 44x systems. Previously only a 44x routine existed. But since this system reset via the debug control register is common for 40x and 44x let's share this code for all those platforms in ppc4xx_soc.c. This patch also enables CONFIG_4xx_SOC for all 40x and 44x platforms. Tested on Kilauea (405EX) and Canyonlands (440EX). Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
126 lines
3.1 KiB
C
126 lines
3.1 KiB
C
/*
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* Architecture- / platform-specific boot-time initialization code for
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* IBM PowerPC 4xx based boards. Adapted from original
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* code by Gary Thomas, Cort Dougan <cort@fsmlabs.com>, and Dan Malek
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* <dan@net4x.com>.
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*
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* Copyright(c) 1999-2000 Grant Erickson <grant@lcse.umn.edu>
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*
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* Rewritten and ported to the merged powerpc tree:
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* Copyright 2007 IBM Corporation
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* Josh Boyer <jwboyer@linux.vnet.ibm.com>
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*
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* Adapted to EP405 by Ben. Herrenschmidt <benh@kernel.crashing.org>
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*
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* TODO: Wire up the PCI IRQ mux and the southbridge interrupts
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*
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* 2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/time.h>
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#include <asm/uic.h>
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#include <asm/pci-bridge.h>
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#include <asm/ppc4xx.h>
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static struct device_node *bcsr_node;
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static void __iomem *bcsr_regs;
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/* BCSR registers */
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#define BCSR_ID 0
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#define BCSR_PCI_CTRL 1
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#define BCSR_FLASH_NV_POR_CTRL 2
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#define BCSR_FENET_UART_CTRL 3
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#define BCSR_PCI_IRQ 4
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#define BCSR_XIRQ_SELECT 5
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#define BCSR_XIRQ_ROUTING 6
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#define BCSR_XIRQ_STATUS 7
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#define BCSR_XIRQ_STATUS2 8
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#define BCSR_SW_STAT_LED_CTRL 9
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#define BCSR_GPIO_IRQ_PAR_CTRL 10
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/* there's more, can't be bothered typing them tho */
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static __initdata struct of_device_id ep405_of_bus[] = {
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{ .compatible = "ibm,plb3", },
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{ .compatible = "ibm,opb", },
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{ .compatible = "ibm,ebc", },
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{},
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};
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static int __init ep405_device_probe(void)
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{
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of_platform_bus_probe(NULL, ep405_of_bus, NULL);
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return 0;
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}
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machine_device_initcall(ep405, ep405_device_probe);
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static void __init ep405_init_bcsr(void)
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{
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const u8 *irq_routing;
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int i;
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/* Find the bloody thing & map it */
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bcsr_node = of_find_compatible_node(NULL, NULL, "ep405-bcsr");
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if (bcsr_node == NULL) {
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printk(KERN_ERR "EP405 BCSR not found !\n");
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return;
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}
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bcsr_regs = of_iomap(bcsr_node, 0);
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if (bcsr_regs == NULL) {
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printk(KERN_ERR "EP405 BCSR failed to map !\n");
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return;
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}
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/* Get the irq-routing property and apply the routing to the CPLD */
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irq_routing = of_get_property(bcsr_node, "irq-routing", NULL);
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if (irq_routing == NULL)
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return;
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for (i = 0; i < 16; i++) {
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u8 irq = irq_routing[i];
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out_8(bcsr_regs + BCSR_XIRQ_SELECT, i);
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out_8(bcsr_regs + BCSR_XIRQ_ROUTING, irq);
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}
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in_8(bcsr_regs + BCSR_XIRQ_SELECT);
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mb();
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out_8(bcsr_regs + BCSR_GPIO_IRQ_PAR_CTRL, 0xfe);
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}
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static void __init ep405_setup_arch(void)
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{
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/* Find & init the BCSR CPLD */
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ep405_init_bcsr();
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ppc_pci_flags = PPC_PCI_REASSIGN_ALL_RSRC;
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}
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static int __init ep405_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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if (!of_flat_dt_is_compatible(root, "ep405"))
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return 0;
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return 1;
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}
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define_machine(ep405) {
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.name = "EP405",
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.probe = ep405_probe,
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.setup_arch = ep405_setup_arch,
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.progress = udbg_progress,
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.init_IRQ = uic_init_tree,
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.get_irq = uic_get_irq,
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.restart = ppc4xx_reset_system,
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.calibrate_decr = generic_calibrate_decr,
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};
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