3292beb340
This patch changes fields in cpustat from a structure, to an u64 array. Math gets easier, and the code is more flexible. Signed-off-by: Glauber Costa <glommer@parallels.com> Reviewed-by: KAMEZAWA Hiroyuki <kamezawa.hiroyu@jp.fujitsu.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Paul Tuner <pjt@google.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1322498719-2255-2-git-send-email-glommer@parallels.com Signed-off-by: Ingo Molnar <mingo@elte.hu>
454 lines
11 KiB
C
454 lines
11 KiB
C
/*
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* Copyright (C) 1994 Linus Torvalds
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*
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* Pentium III FXSR, SSE support
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* General FPU state handling cleanups
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* Gareth Hughes <gareth@valinux.com>, May 2000
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* x86-64 work by Andi Kleen 2002
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*/
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#ifndef _ASM_X86_I387_H
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#define _ASM_X86_I387_H
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#ifndef __ASSEMBLY__
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#include <linux/sched.h>
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#include <linux/kernel_stat.h>
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#include <linux/regset.h>
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#include <linux/hardirq.h>
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#include <linux/slab.h>
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#include <asm/asm.h>
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#include <asm/cpufeature.h>
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#include <asm/processor.h>
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#include <asm/sigcontext.h>
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#include <asm/user.h>
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#include <asm/uaccess.h>
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#include <asm/xsave.h>
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extern unsigned int sig_xstate_size;
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extern void fpu_init(void);
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extern void mxcsr_feature_mask_init(void);
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extern int init_fpu(struct task_struct *child);
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extern asmlinkage void math_state_restore(void);
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extern void __math_state_restore(void);
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extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
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extern user_regset_active_fn fpregs_active, xfpregs_active;
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extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get,
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xstateregs_get;
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extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set,
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xstateregs_set;
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/*
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* xstateregs_active == fpregs_active. Please refer to the comment
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* at the definition of fpregs_active.
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*/
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#define xstateregs_active fpregs_active
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extern struct _fpx_sw_bytes fx_sw_reserved;
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#ifdef CONFIG_IA32_EMULATION
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extern unsigned int sig_xstate_ia32_size;
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extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
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struct _fpstate_ia32;
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struct _xstate_ia32;
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extern int save_i387_xstate_ia32(void __user *buf);
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extern int restore_i387_xstate_ia32(void __user *buf);
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#endif
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#ifdef CONFIG_MATH_EMULATION
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extern void finit_soft_fpu(struct i387_soft_struct *soft);
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#else
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static inline void finit_soft_fpu(struct i387_soft_struct *soft) {}
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#endif
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#define X87_FSW_ES (1 << 7) /* Exception Summary */
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static __always_inline __pure bool use_xsaveopt(void)
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{
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return static_cpu_has(X86_FEATURE_XSAVEOPT);
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}
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static __always_inline __pure bool use_xsave(void)
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{
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return static_cpu_has(X86_FEATURE_XSAVE);
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}
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static __always_inline __pure bool use_fxsr(void)
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{
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return static_cpu_has(X86_FEATURE_FXSR);
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}
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extern void __sanitize_i387_state(struct task_struct *);
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static inline void sanitize_i387_state(struct task_struct *tsk)
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{
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if (!use_xsaveopt())
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return;
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__sanitize_i387_state(tsk);
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}
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#ifdef CONFIG_X86_64
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static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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{
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int err;
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/* See comment in fxsave() below. */
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#ifdef CONFIG_AS_FXSAVEQ
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asm volatile("1: fxrstorq %[fx]\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err)
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: [fx] "m" (*fx), "0" (0));
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#else
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asm volatile("1: rex64/fxrstor (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err)
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: [fx] "R" (fx), "m" (*fx), "0" (0));
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#endif
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return err;
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}
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static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
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{
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int err;
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/*
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* Clear the bytes not touched by the fxsave and reserved
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* for the SW usage.
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*/
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err = __clear_user(&fx->sw_reserved,
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sizeof(struct _fpx_sw_bytes));
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if (unlikely(err))
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return -EFAULT;
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/* See comment in fxsave() below. */
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#ifdef CONFIG_AS_FXSAVEQ
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asm volatile("1: fxsaveq %[fx]\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err), [fx] "=m" (*fx)
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: "0" (0));
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#else
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asm volatile("1: rex64/fxsave (%[fx])\n\t"
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"2:\n"
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".section .fixup,\"ax\"\n"
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"3: movl $-1,%[err]\n"
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" jmp 2b\n"
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".previous\n"
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_ASM_EXTABLE(1b, 3b)
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: [err] "=r" (err), "=m" (*fx)
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: [fx] "R" (fx), "0" (0));
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#endif
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if (unlikely(err) &&
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__clear_user(fx, sizeof(struct i387_fxsave_struct)))
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err = -EFAULT;
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/* No need to clear here because the caller clears USED_MATH */
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return err;
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}
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static inline void fpu_fxsave(struct fpu *fpu)
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{
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/* Using "rex64; fxsave %0" is broken because, if the memory operand
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uses any extended registers for addressing, a second REX prefix
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will be generated (to the assembler, rex64 followed by semicolon
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is a separate instruction), and hence the 64-bitness is lost. */
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#ifdef CONFIG_AS_FXSAVEQ
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/* Using "fxsaveq %0" would be the ideal choice, but is only supported
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starting with gas 2.16. */
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__asm__ __volatile__("fxsaveq %0"
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: "=m" (fpu->state->fxsave));
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#else
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/* Using, as a workaround, the properly prefixed form below isn't
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accepted by any binutils version so far released, complaining that
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the same type of prefix is used twice if an extended register is
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needed for addressing (fix submitted to mainline 2005-11-21).
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asm volatile("rex64/fxsave %0"
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: "=m" (fpu->state->fxsave));
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This, however, we can work around by forcing the compiler to select
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an addressing mode that doesn't require extended registers. */
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asm volatile("rex64/fxsave (%[fx])"
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: "=m" (fpu->state->fxsave)
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: [fx] "R" (&fpu->state->fxsave));
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#endif
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}
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#else /* CONFIG_X86_32 */
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/* perform fxrstor iff the processor has extended states, otherwise frstor */
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static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
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{
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/*
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* The "nop" is needed to make the instructions the same
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* length.
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*/
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alternative_input(
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"nop ; frstor %1",
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"fxrstor %1",
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X86_FEATURE_FXSR,
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"m" (*fx));
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return 0;
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}
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static inline void fpu_fxsave(struct fpu *fpu)
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{
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asm volatile("fxsave %[fx]"
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: [fx] "=m" (fpu->state->fxsave));
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}
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#endif /* CONFIG_X86_64 */
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/* We need a safe address that is cheap to find and that is already
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in L1 during context switch. The best choices are unfortunately
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different for UP and SMP */
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#ifdef CONFIG_SMP
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#define safe_address (__per_cpu_offset[0])
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#else
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#define safe_address (__get_cpu_var(kernel_cpustat).cpustat[CPUTIME_USER])
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#endif
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/*
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* These must be called with preempt disabled
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*/
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static inline void fpu_save_init(struct fpu *fpu)
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{
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if (use_xsave()) {
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fpu_xsave(fpu);
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/*
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* xsave header may indicate the init state of the FP.
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*/
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if (!(fpu->state->xsave.xsave_hdr.xstate_bv & XSTATE_FP))
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return;
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} else if (use_fxsr()) {
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fpu_fxsave(fpu);
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} else {
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asm volatile("fnsave %[fx]; fwait"
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: [fx] "=m" (fpu->state->fsave));
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return;
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}
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if (unlikely(fpu->state->fxsave.swd & X87_FSW_ES))
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asm volatile("fnclex");
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/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
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is pending. Clear the x87 state here by setting it to fixed
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values. safe_address is a random variable that should be in L1 */
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alternative_input(
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ASM_NOP8 ASM_NOP2,
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"emms\n\t" /* clear stack tags */
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"fildl %P[addr]", /* set F?P to defined value */
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X86_FEATURE_FXSAVE_LEAK,
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[addr] "m" (safe_address));
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}
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static inline void __save_init_fpu(struct task_struct *tsk)
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{
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fpu_save_init(&tsk->thread.fpu);
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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}
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static inline int fpu_fxrstor_checking(struct fpu *fpu)
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{
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return fxrstor_checking(&fpu->state->fxsave);
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}
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static inline int fpu_restore_checking(struct fpu *fpu)
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{
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if (use_xsave())
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return fpu_xrstor_checking(fpu);
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else
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return fpu_fxrstor_checking(fpu);
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}
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static inline int restore_fpu_checking(struct task_struct *tsk)
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{
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return fpu_restore_checking(&tsk->thread.fpu);
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}
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/*
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* Signal frame handlers...
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*/
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extern int save_i387_xstate(void __user *buf);
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extern int restore_i387_xstate(void __user *buf);
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static inline void __unlazy_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_USEDFPU) {
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__save_init_fpu(tsk);
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stts();
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} else
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tsk->fpu_counter = 0;
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}
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static inline void __clear_fpu(struct task_struct *tsk)
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{
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if (task_thread_info(tsk)->status & TS_USEDFPU) {
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/* Ignore delayed exceptions from user space */
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asm volatile("1: fwait\n"
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"2:\n"
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_ASM_EXTABLE(1b, 2b));
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task_thread_info(tsk)->status &= ~TS_USEDFPU;
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stts();
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}
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}
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static inline void kernel_fpu_begin(void)
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{
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struct thread_info *me = current_thread_info();
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preempt_disable();
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if (me->status & TS_USEDFPU)
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__save_init_fpu(me->task);
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else
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clts();
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}
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static inline void kernel_fpu_end(void)
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{
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stts();
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preempt_enable();
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}
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static inline bool irq_fpu_usable(void)
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{
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struct pt_regs *regs;
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return !in_interrupt() || !(regs = get_irq_regs()) || \
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user_mode(regs) || (read_cr0() & X86_CR0_TS);
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}
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/*
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* Some instructions like VIA's padlock instructions generate a spurious
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* DNA fault but don't modify SSE registers. And these instructions
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* get used from interrupt context as well. To prevent these kernel instructions
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* in interrupt context interacting wrongly with other user/kernel fpu usage, we
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* should use them only in the context of irq_ts_save/restore()
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*/
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static inline int irq_ts_save(void)
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{
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/*
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* If in process context and not atomic, we can take a spurious DNA fault.
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* Otherwise, doing clts() in process context requires disabling preemption
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* or some heavy lifting like kernel_fpu_begin()
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*/
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if (!in_atomic())
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return 0;
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if (read_cr0() & X86_CR0_TS) {
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clts();
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return 1;
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}
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return 0;
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}
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static inline void irq_ts_restore(int TS_state)
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{
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if (TS_state)
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stts();
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}
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/*
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* These disable preemption on their own and are safe
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*/
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static inline void save_init_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__save_init_fpu(tsk);
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stts();
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preempt_enable();
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}
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static inline void unlazy_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__unlazy_fpu(tsk);
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preempt_enable();
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}
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static inline void clear_fpu(struct task_struct *tsk)
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{
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preempt_disable();
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__clear_fpu(tsk);
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preempt_enable();
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}
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/*
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* i387 state interaction
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*/
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static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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return tsk->thread.fpu.state->fxsave.cwd;
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} else {
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return (unsigned short)tsk->thread.fpu.state->fsave.cwd;
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}
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}
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static inline unsigned short get_fpu_swd(struct task_struct *tsk)
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{
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if (cpu_has_fxsr) {
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return tsk->thread.fpu.state->fxsave.swd;
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} else {
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return (unsigned short)tsk->thread.fpu.state->fsave.swd;
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}
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}
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static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
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{
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if (cpu_has_xmm) {
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return tsk->thread.fpu.state->fxsave.mxcsr;
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} else {
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return MXCSR_DEFAULT;
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}
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}
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static bool fpu_allocated(struct fpu *fpu)
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{
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return fpu->state != NULL;
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}
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static inline int fpu_alloc(struct fpu *fpu)
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{
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if (fpu_allocated(fpu))
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return 0;
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fpu->state = kmem_cache_alloc(task_xstate_cachep, GFP_KERNEL);
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if (!fpu->state)
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return -ENOMEM;
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WARN_ON((unsigned long)fpu->state & 15);
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return 0;
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}
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static inline void fpu_free(struct fpu *fpu)
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{
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if (fpu->state) {
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kmem_cache_free(task_xstate_cachep, fpu->state);
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fpu->state = NULL;
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}
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}
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static inline void fpu_copy(struct fpu *dst, struct fpu *src)
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{
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memcpy(dst->state, src->state, xstate_size);
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}
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extern void fpu_finit(struct fpu *fpu);
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_X86_I387_H */
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