a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
107 lines
3.4 KiB
C
107 lines
3.4 KiB
C
/*
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* arch/arm/plat-omap/include/mach/tc.h
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*
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* OMAP Traffic Controller
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*
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* Copyright (C) 2004 Nokia Corporation
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* Author: Imre Deak <imre.deak@nokia.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#ifndef __ASM_ARCH_TC_H
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#define __ASM_ARCH_TC_H
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#define TCMIF_BASE 0xfffecc00
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#define OMAP_TC_OCPT1_PRIOR (TCMIF_BASE + 0x00)
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#define OMAP_TC_EMIFS_PRIOR (TCMIF_BASE + 0x04)
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#define OMAP_TC_EMIFF_PRIOR (TCMIF_BASE + 0x08)
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#define EMIFS_CONFIG (TCMIF_BASE + 0x0c)
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#define EMIFS_CS0_CONFIG (TCMIF_BASE + 0x10)
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#define EMIFS_CS1_CONFIG (TCMIF_BASE + 0x14)
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#define EMIFS_CS2_CONFIG (TCMIF_BASE + 0x18)
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#define EMIFS_CS3_CONFIG (TCMIF_BASE + 0x1c)
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#define EMIFF_SDRAM_CONFIG (TCMIF_BASE + 0x20)
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#define EMIFF_MRS (TCMIF_BASE + 0x24)
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#define TC_TIMEOUT1 (TCMIF_BASE + 0x28)
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#define TC_TIMEOUT2 (TCMIF_BASE + 0x2c)
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#define TC_TIMEOUT3 (TCMIF_BASE + 0x30)
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#define TC_ENDIANISM (TCMIF_BASE + 0x34)
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#define EMIFF_SDRAM_CONFIG_2 (TCMIF_BASE + 0x3c)
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#define EMIF_CFG_DYNAMIC_WS (TCMIF_BASE + 0x40)
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#define EMIFS_ACS0 (TCMIF_BASE + 0x50)
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#define EMIFS_ACS1 (TCMIF_BASE + 0x54)
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#define EMIFS_ACS2 (TCMIF_BASE + 0x58)
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#define EMIFS_ACS3 (TCMIF_BASE + 0x5c)
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#define OMAP_TC_OCPT2_PRIOR (TCMIF_BASE + 0xd0)
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/* external EMIFS chipselect regions */
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#define OMAP_CS0_PHYS 0x00000000
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#define OMAP_CS0_SIZE SZ_64M
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#define OMAP_CS1_PHYS 0x04000000
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#define OMAP_CS1_SIZE SZ_64M
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#define OMAP_CS1A_PHYS OMAP_CS1_PHYS
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#define OMAP_CS1A_SIZE SZ_32M
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#define OMAP_CS1B_PHYS (OMAP_CS1A_PHYS + OMAP_CS1A_SIZE)
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#define OMAP_CS1B_SIZE SZ_32M
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#define OMAP_CS2_PHYS 0x08000000
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#define OMAP_CS2_SIZE SZ_64M
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#define OMAP_CS2A_PHYS OMAP_CS2_PHYS
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#define OMAP_CS2A_SIZE SZ_32M
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#define OMAP_CS2B_PHYS (OMAP_CS2A_PHYS + OMAP_CS2A_SIZE)
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#define OMAP_CS2B_SIZE SZ_32M
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#define OMAP_CS3_PHYS 0x0c000000
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#define OMAP_CS3_SIZE SZ_64M
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#ifndef __ASSEMBLER__
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/* EMIF Slow Interface Configuration Register */
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#define OMAP_EMIFS_CONFIG_FR (1 << 4)
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#define OMAP_EMIFS_CONFIG_PDE (1 << 3)
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#define OMAP_EMIFS_CONFIG_PWD_EN (1 << 2)
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#define OMAP_EMIFS_CONFIG_BM (1 << 1)
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#define OMAP_EMIFS_CONFIG_WP (1 << 0)
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#define EMIFS_CCS(n) (EMIFS_CS0_CONFIG + (4 * (n)))
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#define EMIFS_ACS(n) (EMIFS_ACS0 + (4 * (n)))
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/* Almost all documentation for chip and board memory maps assumes
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* BM is clear. Most devel boards have a switch to control booting
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* from NOR flash (using external chipselect 3) rather than mask ROM,
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* which uses BM to interchange the physical CS0 and CS3 addresses.
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*/
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static inline u32 omap_cs0_phys(void)
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{
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return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
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? OMAP_CS3_PHYS : 0;
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}
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static inline u32 omap_cs3_phys(void)
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{
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return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
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? 0 : OMAP_CS3_PHYS;
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}
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#endif /* __ASSEMBLER__ */
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#endif /* __ASM_ARCH_TC_H */
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