1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
574 lines
15 KiB
C
574 lines
15 KiB
C
/*
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* SiS 300/630/730/540/315/550/[M]650/651/[M]661[FM]X/740/[M]741[GX]/330/[M]760[GX]
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* frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3
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*
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* Copyright (C) 2001-2004 Thomas Winischhofer, Vienna, Austria.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the named License,
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* or any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
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*/
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#ifndef _SIS_H
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#define _SIS_H
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#include <linux/config.h>
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#include <linux/version.h>
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#include "osdef.h"
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
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#include <video/sisfb.h>
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#else
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#include <linux/sisfb.h>
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#endif
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#include "vgatypes.h"
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#include "vstruct.h"
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#define VER_MAJOR 1
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#define VER_MINOR 7
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#define VER_LEVEL 17
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#undef SIS_CONFIG_COMPAT
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
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#include <linux/spinlock.h>
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#ifdef CONFIG_COMPAT
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#include <linux/ioctl32.h>
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#define SIS_CONFIG_COMPAT
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#endif
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#elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,19)
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#ifdef __x86_64__
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/* Shouldn't we check for CONFIG_IA32_EMULATION here? */
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#include <asm/ioctl32.h>
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#define SIS_CONFIG_COMPAT
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#endif
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#endif
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#if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,8)
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#define SIS_IOTYPE1 void __iomem
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#define SIS_IOTYPE2 __iomem
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#define SISINITSTATIC static
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#else
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#define SIS_IOTYPE1 unsigned char
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#define SIS_IOTYPE2
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#define SISINITSTATIC
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#endif
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#undef SISFBDEBUG
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#ifdef SISFBDEBUG
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#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
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#define TWDEBUG(x) printk(KERN_INFO x "\n");
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#else
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#define DPRINTK(fmt, args...)
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#define TWDEBUG(x)
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#endif
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#define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)
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/* To be included in pci_ids.h */
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#ifndef PCI_DEVICE_ID_SI_650_VGA
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#define PCI_DEVICE_ID_SI_650_VGA 0x6325
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#endif
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#ifndef PCI_DEVICE_ID_SI_650
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#define PCI_DEVICE_ID_SI_650 0x0650
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#endif
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#ifndef PCI_DEVICE_ID_SI_651
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#define PCI_DEVICE_ID_SI_651 0x0651
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#endif
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#ifndef PCI_DEVICE_ID_SI_740
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#define PCI_DEVICE_ID_SI_740 0x0740
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#endif
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#ifndef PCI_DEVICE_ID_SI_330
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#define PCI_DEVICE_ID_SI_330 0x0330
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#endif
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#ifndef PCI_DEVICE_ID_SI_660_VGA
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#define PCI_DEVICE_ID_SI_660_VGA 0x6330
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#endif
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#ifndef PCI_DEVICE_ID_SI_661
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#define PCI_DEVICE_ID_SI_661 0x0661
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#endif
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#ifndef PCI_DEVICE_ID_SI_741
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#define PCI_DEVICE_ID_SI_741 0x0741
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#endif
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#ifndef PCI_DEVICE_ID_SI_660
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#define PCI_DEVICE_ID_SI_660 0x0660
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#endif
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#ifndef PCI_DEVICE_ID_SI_760
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#define PCI_DEVICE_ID_SI_760 0x0760
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#endif
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/* To be included in fb.h */
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#ifndef FB_ACCEL_SIS_GLAMOUR_2
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#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 65x, 740, 661, 741 */
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#endif
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#ifndef FB_ACCEL_SIS_XABRE
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#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre"), 760 */
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#endif
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#define MAX_ROM_SCAN 0x10000
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/* ivideo->caps */
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#define HW_CURSOR_CAP 0x80
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#define TURBO_QUEUE_CAP 0x40
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#define AGP_CMD_QUEUE_CAP 0x20
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#define VM_CMD_QUEUE_CAP 0x10
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#define MMIO_CMD_QUEUE_CAP 0x08
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/* For 300 series */
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#define TURBO_QUEUE_AREA_SIZE 0x80000 /* 512K */
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#define HW_CURSOR_AREA_SIZE_300 0x1000 /* 4K */
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/* For 315/Xabre series */
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#define COMMAND_QUEUE_AREA_SIZE 0x80000 /* 512K */
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#define COMMAND_QUEUE_THRESHOLD 0x1F
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#define HW_CURSOR_AREA_SIZE_315 0x4000 /* 16K */
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#define SIS_OH_ALLOC_SIZE 4000
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#define SENTINEL 0x7fffffff
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#define SEQ_ADR 0x14
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#define SEQ_DATA 0x15
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#define DAC_ADR 0x18
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#define DAC_DATA 0x19
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#define CRTC_ADR 0x24
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#define CRTC_DATA 0x25
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#define DAC2_ADR (0x16-0x30)
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#define DAC2_DATA (0x17-0x30)
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#define VB_PART1_ADR (0x04-0x30)
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#define VB_PART1_DATA (0x05-0x30)
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#define VB_PART2_ADR (0x10-0x30)
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#define VB_PART2_DATA (0x11-0x30)
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#define VB_PART3_ADR (0x12-0x30)
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#define VB_PART3_DATA (0x13-0x30)
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#define VB_PART4_ADR (0x14-0x30)
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#define VB_PART4_DATA (0x15-0x30)
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#define SISSR ivideo->SiS_Pr.SiS_P3c4
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#define SISCR ivideo->SiS_Pr.SiS_P3d4
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#define SISDACA ivideo->SiS_Pr.SiS_P3c8
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#define SISDACD ivideo->SiS_Pr.SiS_P3c9
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#define SISPART1 ivideo->SiS_Pr.SiS_Part1Port
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#define SISPART2 ivideo->SiS_Pr.SiS_Part2Port
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#define SISPART3 ivideo->SiS_Pr.SiS_Part3Port
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#define SISPART4 ivideo->SiS_Pr.SiS_Part4Port
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#define SISPART5 ivideo->SiS_Pr.SiS_Part5Port
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#define SISDAC2A SISPART5
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#define SISDAC2D (SISPART5 + 1)
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#define SISMISCR (ivideo->SiS_Pr.RelIO + 0x1c)
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#define SISMISCW ivideo->SiS_Pr.SiS_P3c2
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#define SISINPSTAT (ivideo->SiS_Pr.RelIO + 0x2a)
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#define SISPEL ivideo->SiS_Pr.SiS_P3c6
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#define IND_SIS_PASSWORD 0x05 /* SRs */
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#define IND_SIS_COLOR_MODE 0x06
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#define IND_SIS_RAMDAC_CONTROL 0x07
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#define IND_SIS_DRAM_SIZE 0x14
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#define IND_SIS_MODULE_ENABLE 0x1E
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#define IND_SIS_PCI_ADDRESS_SET 0x20
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#define IND_SIS_TURBOQUEUE_ADR 0x26
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#define IND_SIS_TURBOQUEUE_SET 0x27
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#define IND_SIS_POWER_ON_TRAP 0x38
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#define IND_SIS_POWER_ON_TRAP2 0x39
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#define IND_SIS_CMDQUEUE_SET 0x26
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#define IND_SIS_CMDQUEUE_THRESHOLD 0x27
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#define IND_SIS_AGP_IO_PAD 0x48
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#define SIS_CRT2_WENABLE_300 0x24 /* Part1 */
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#define SIS_CRT2_WENABLE_315 0x2F
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#define SIS_PASSWORD 0x86 /* SR05 */
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#define SIS_INTERLACED_MODE 0x20 /* SR06 */
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#define SIS_8BPP_COLOR_MODE 0x0
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#define SIS_15BPP_COLOR_MODE 0x1
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#define SIS_16BPP_COLOR_MODE 0x2
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#define SIS_32BPP_COLOR_MODE 0x4
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#define SIS_ENABLE_2D 0x40 /* SR1E */
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#define SIS_MEM_MAP_IO_ENABLE 0x01 /* SR20 */
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#define SIS_PCI_ADDR_ENABLE 0x80
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#define SIS_AGP_CMDQUEUE_ENABLE 0x80 /* 315/330 series SR26 */
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#define SIS_VRAM_CMDQUEUE_ENABLE 0x40
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#define SIS_MMIO_CMD_ENABLE 0x20
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#define SIS_CMD_QUEUE_SIZE_512k 0x00
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#define SIS_CMD_QUEUE_SIZE_1M 0x04
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#define SIS_CMD_QUEUE_SIZE_2M 0x08
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#define SIS_CMD_QUEUE_SIZE_4M 0x0C
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#define SIS_CMD_QUEUE_RESET 0x01
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#define SIS_CMD_AUTO_CORR 0x02
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#define SIS_SIMULTANEOUS_VIEW_ENABLE 0x01 /* CR30 */
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#define SIS_MODE_SELECT_CRT2 0x02
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#define SIS_VB_OUTPUT_COMPOSITE 0x04
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#define SIS_VB_OUTPUT_SVIDEO 0x08
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#define SIS_VB_OUTPUT_SCART 0x10
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#define SIS_VB_OUTPUT_LCD 0x20
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#define SIS_VB_OUTPUT_CRT2 0x40
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#define SIS_VB_OUTPUT_HIVISION 0x80
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#define SIS_VB_OUTPUT_DISABLE 0x20 /* CR31 */
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#define SIS_DRIVER_MODE 0x40
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#define SIS_VB_COMPOSITE 0x01 /* CR32 */
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#define SIS_VB_SVIDEO 0x02
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#define SIS_VB_SCART 0x04
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#define SIS_VB_LCD 0x08
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#define SIS_VB_CRT2 0x10
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#define SIS_CRT1 0x20
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#define SIS_VB_HIVISION 0x40
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#define SIS_VB_YPBPR 0x80
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#define SIS_VB_TV (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \
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SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR)
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#define SIS_EXTERNAL_CHIP_MASK 0x0E /* CR37 (< SiS 660) */
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#define SIS_EXTERNAL_CHIP_SIS301 0x01 /* in CR37 << 1 ! */
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#define SIS_EXTERNAL_CHIP_LVDS 0x02
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#define SIS_EXTERNAL_CHIP_TRUMPION 0x03
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#define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL 0x04
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#define SIS_EXTERNAL_CHIP_CHRONTEL 0x05
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#define SIS310_EXTERNAL_CHIP_LVDS 0x02
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#define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03
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#define SIS_AGP_2X 0x20 /* CR48 */
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#define HW_DEVICE_EXTENSION SIS_HW_INFO
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#define PHW_DEVICE_EXTENSION PSIS_HW_INFO
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/* I/O port access macros */
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#define inSISREG(base) inb(base)
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#define outSISREG(base,val) outb(val,base)
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#define orSISREG(base,val) \
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do { \
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u8 __Temp = inSISREG(base); \
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outSISREG(base, __Temp | (val)); \
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} while (0)
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#define andSISREG(base,val) \
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do { \
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u8 __Temp = inSISREG(base); \
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outSISREG(base, __Temp & (val)); \
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} while (0)
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#define inSISIDXREG(base,idx,var) \
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do { \
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outSISREG(base, idx); \
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var = inSISREG((base)+1); \
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} while (0)
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#define outSISIDXREG(base,idx,val) \
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do { \
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outSISREG(base, idx); \
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outSISREG((base)+1, val); \
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} while (0)
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#define orSISIDXREG(base,idx,val) \
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do { \
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u8 __Temp; \
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outSISREG(base, idx); \
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__Temp = inSISREG((base)+1) | (val); \
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outSISREG((base)+1, __Temp); \
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} while (0)
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#define andSISIDXREG(base,idx,and) \
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do { \
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u8 __Temp; \
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outSISREG(base, idx); \
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__Temp = inSISREG((base)+1) & (and); \
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outSISREG((base)+1, __Temp); \
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} while (0)
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#define setSISIDXREG(base,idx,and,or) \
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do { \
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u8 __Temp; \
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outSISREG(base, idx); \
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__Temp = (inSISREG((base)+1) & (and)) | (or); \
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outSISREG((base)+1, __Temp); \
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} while (0)
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/* MMIO access macros */
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#define MMIO_IN8(base, offset) readb((base+offset))
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#define MMIO_IN16(base, offset) readw((base+offset))
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#define MMIO_IN32(base, offset) readl((base+offset))
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#define MMIO_OUT8(base, offset, val) writeb(((u8)(val)), (base+offset))
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#define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset))
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#define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))
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/* Queue control MMIO registers */
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#define Q_BASE_ADDR 0x85C0 /* Base address of software queue */
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#define Q_WRITE_PTR 0x85C4 /* Current write pointer */
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#define Q_READ_PTR 0x85C8 /* Current read pointer */
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#define Q_STATUS 0x85CC /* queue status */
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#define MMIO_QUEUE_PHYBASE Q_BASE_ADDR
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#define MMIO_QUEUE_WRITEPORT Q_WRITE_PTR
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#define MMIO_QUEUE_READPORT Q_READ_PTR
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#ifndef FB_BLANK_UNBLANK
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#define FB_BLANK_UNBLANK 0
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#endif
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#ifndef FB_BLANK_NORMAL
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#define FB_BLANK_NORMAL 1
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#endif
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#ifndef FB_BLANK_VSYNC_SUSPEND
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#define FB_BLANK_VSYNC_SUSPEND 2
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#endif
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#ifndef FB_BLANK_HSYNC_SUSPEND
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#define FB_BLANK_HSYNC_SUSPEND 3
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#endif
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#ifndef FB_BLANK_POWERDOWN
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#define FB_BLANK_POWERDOWN 4
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#endif
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enum _SIS_LCD_TYPE {
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LCD_INVALID = 0,
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LCD_800x600,
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LCD_1024x768,
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LCD_1280x1024,
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LCD_1280x960,
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LCD_640x480,
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LCD_1600x1200,
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LCD_1920x1440,
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LCD_2048x1536,
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LCD_320x480, /* FSTN */
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LCD_1400x1050,
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LCD_1152x864,
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LCD_1152x768,
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LCD_1280x768,
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LCD_1024x600,
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LCD_640x480_2, /* DSTN */
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LCD_640x480_3, /* DSTN */
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LCD_848x480,
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LCD_1280x800,
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LCD_1680x1050,
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LCD_1280x720,
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LCD_CUSTOM,
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LCD_UNKNOWN
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};
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enum _SIS_CMDTYPE {
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MMIO_CMD = 0,
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AGP_CMD_QUEUE,
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VM_CMD_QUEUE,
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};
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typedef unsigned int SIS_CMDTYPE;
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/* Our "par" */
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struct sis_video_info {
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int cardnumber;
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struct fb_info *memyselfandi;
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SIS_HW_INFO sishw_ext;
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SiS_Private SiS_Pr;
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sisfb_info sisfbinfo; /* For ioctl SISFB_GET_INFO */
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struct fb_var_screeninfo default_var;
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
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struct fb_fix_screeninfo sisfb_fix;
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u32 pseudo_palette[17];
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#endif
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
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struct display sis_disp;
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struct display_switch sisfb_sw;
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struct {
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u16 red, green, blue, pad;
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} sis_palette[256];
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union {
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#ifdef FBCON_HAS_CFB16
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u16 cfb16[16];
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#endif
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#ifdef FBCON_HAS_CFB32
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u32 cfb32[16];
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#endif
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} sis_fbcon_cmap;
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#endif
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struct sisfb_monitor {
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u16 hmin;
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u16 hmax;
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u16 vmin;
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u16 vmax;
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u32 dclockmax;
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u8 feature;
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BOOLEAN datavalid;
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} sisfb_thismonitor;
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int chip_id;
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char myid[40];
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struct pci_dev *nbridge;
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int mni; /* Mode number index */
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
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int currcon;
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#endif
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unsigned long video_size;
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unsigned long video_base;
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unsigned long mmio_size;
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unsigned long mmio_base;
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unsigned long vga_base;
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SIS_IOTYPE1 *video_vbase;
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SIS_IOTYPE1 *mmio_vbase;
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unsigned char *bios_abase;
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int mtrr;
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u32 sisfb_mem;
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u32 sisfb_parm_mem;
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int sisfb_accel;
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int sisfb_ypan;
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int sisfb_max;
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int sisfb_userom;
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int sisfb_useoem;
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int sisfb_mode_idx;
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int sisfb_parm_rate;
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int sisfb_crt1off;
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int sisfb_forcecrt1;
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int sisfb_crt2type;
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int sisfb_crt2flags;
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int sisfb_dstn;
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int sisfb_fstn;
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int sisfb_tvplug;
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int sisfb_tvstd;
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int sisfb_filter;
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int sisfb_nocrt2rate;
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
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int sisfb_inverse;
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#endif
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u32 heapstart; /* offset */
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SIS_IOTYPE1 *sisfb_heap_start; /* address */
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SIS_IOTYPE1 *sisfb_heap_end; /* address */
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u32 sisfb_heap_size;
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int havenoheap;
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#if 0
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SIS_HEAP sisfb_heap;
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#endif
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int video_bpp;
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int video_cmap_len;
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int video_width;
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int video_height;
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unsigned int refresh_rate;
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unsigned int chip;
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u8 revision_id;
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int video_linelength; /* real pitch */
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int scrnpitchCRT1; /* pitch regarding interlace */
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u16 DstColor; /* For 2d acceleration */
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u32 SiS310_AccelDepth;
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u32 CommandReg;
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int cmdqueuelength;
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spinlock_t lockaccel; /* Do not use outside of kernel! */
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unsigned int pcibus;
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unsigned int pcislot;
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unsigned int pcifunc;
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int accel;
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u16 subsysvendor;
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u16 subsysdevice;
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u32 vbflags; /* Replacing deprecated stuff from above */
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u32 currentvbflags;
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int lcdxres, lcdyres;
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int lcddefmodeidx, tvdefmodeidx, defmodeidx;
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u32 CRT2LCDType; /* defined in "SIS_LCD_TYPE" */
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int current_bpp;
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int current_width;
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int current_height;
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int current_htotal;
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int current_vtotal;
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int current_linelength;
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__u32 current_pixclock;
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int current_refresh_rate;
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u8 mode_no;
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u8 rate_idx;
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int modechanged;
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unsigned char modeprechange;
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#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
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u8 sisfb_lastrates[128];
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#endif
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int newrom;
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int registered;
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int warncount;
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int sisvga_engine;
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int hwcursor_size;
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int CRT2_write_enable;
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u8 caps;
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u8 detectedpdc;
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u8 detectedpdca;
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u8 detectedlcda;
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SIS_IOTYPE1 *hwcursor_vbase;
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int chronteltype;
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int tvxpos, tvypos;
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u8 p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02;
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int tvx, tvy;
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u8 sisfblocked;
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|
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struct sis_video_info *next;
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};
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typedef struct _SIS_OH {
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struct _SIS_OH *poh_next;
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struct _SIS_OH *poh_prev;
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u32 offset;
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u32 size;
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} SIS_OH;
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|
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typedef struct _SIS_OHALLOC {
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struct _SIS_OHALLOC *poha_next;
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SIS_OH aoh[1];
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} SIS_OHALLOC;
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|
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typedef struct _SIS_HEAP {
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SIS_OH oh_free;
|
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SIS_OH oh_used;
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SIS_OH *poh_freelist;
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SIS_OHALLOC *poha_chain;
|
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u32 max_freesize;
|
|
struct sis_video_info *vinfo;
|
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} SIS_HEAP;
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|
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#endif
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