49cbe78637
"""The Marvell® PXA168 processor is the first in a family of application processors targeted at mass market opportunities in computing and consumer devices. It balances high computing and multimedia performance with low power consumption to support extended battery life, and includes a wealth of integrated peripherals to reduce overall BOM cost .... """ See http://www.marvell.com/featured/pxa168.jsp for more information. 1. Marvell Mohawk core is a hybrid of xscale3 and its own ARM core, there are many enhancements like instructions for flushing the whole D-cache, and so on 2. Clock reuses Russell's common clkdev, and added the basic support for UART1/2. 3. Devices are a bit different from the 'mach-pxa' way, the platform devices are now dynamically allocated only when necessary (i.e. when pxa_register_device() is called). Description for each device are stored in an array of 'struct pxa_device_desc'. Now that: a. this array of device description is marked with __initdata and can be freed up system is fully up b. which means board code has to add all needed devices early in his initializing function c. platform specific data can now be marked as __initdata since they are allocated and copied by platform_device_add_data() 4. only the basic UART1/2/3 are added, more devices will come later. Signed-off-by: Jason Chagas <chagas@marvell.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
45 lines
1.3 KiB
C
45 lines
1.3 KiB
C
/*
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* linux/arch/arm/mach-mmp/include/mach/regs-timers.h
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*
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* Timers Module
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_MACH_REGS_TIMERS_H
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#define __ASM_MACH_REGS_TIMERS_H
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#include <mach/addr-map.h>
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#define TIMERS1_VIRT_BASE (APB_VIRT_BASE + 0x14000)
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#define TIMERS2_VIRT_BASE (APB_VIRT_BASE + 0x16000)
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#define TMR_CCR (0x0000)
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#define TMR_TN_MM(n, m) (0x0004 + ((n) << 3) + (((n) + (m)) << 2))
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#define TMR_CR(n) (0x0028 + ((n) << 2))
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#define TMR_SR(n) (0x0034 + ((n) << 2))
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#define TMR_IER(n) (0x0040 + ((n) << 2))
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#define TMR_PLVR(n) (0x004c + ((n) << 2))
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#define TMR_PLCR(n) (0x0058 + ((n) << 2))
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#define TMR_WMER (0x0064)
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#define TMR_WMR (0x0068)
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#define TMR_WVR (0x006c)
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#define TMR_WSR (0x0070)
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#define TMR_ICR(n) (0x0074 + ((n) << 2))
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#define TMR_WICR (0x0080)
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#define TMR_CER (0x0084)
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#define TMR_CMR (0x0088)
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#define TMR_ILR(n) (0x008c + ((n) << 2))
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#define TMR_WCR (0x0098)
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#define TMR_WFAR (0x009c)
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#define TMR_WSAR (0x00A0)
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#define TMR_CVWR(n) (0x00A4 + ((n) << 2))
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#define TMR_CCR_CS_0(x) (((x) & 0x3) << 0)
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#define TMR_CCR_CS_1(x) (((x) & 0x7) << 2)
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#define TMR_CCR_CS_2(x) (((x) & 0x3) << 5)
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#endif /* __ASM_MACH_REGS_TIMERS_H */
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