1a410d8830
Add oprofile cpu_type to cpu feature struct. Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
164 lines
5.1 KiB
C
164 lines
5.1 KiB
C
/*
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* include/asm-ppc64/cputable.h
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*
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* Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
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*
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* Modifications for ppc64:
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* Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __ASM_PPC_CPUTABLE_H
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#define __ASM_PPC_CPUTABLE_H
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#include <linux/config.h>
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#include <asm/page.h> /* for ASM_CONST */
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/* Exposed to userland CPU features - Must match ppc32 definitions */
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#define PPC_FEATURE_32 0x80000000
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#define PPC_FEATURE_64 0x40000000
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#define PPC_FEATURE_601_INSTR 0x20000000
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#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
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#define PPC_FEATURE_HAS_FPU 0x08000000
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#define PPC_FEATURE_HAS_MMU 0x04000000
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#define PPC_FEATURE_HAS_4xxMAC 0x02000000
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#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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/* This structure can grow, it's real size is used by head.S code
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* via the mkdefs mechanism.
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*/
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struct cpu_spec;
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typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
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struct cpu_spec {
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/* CPU is matched via (PVR & pvr_mask) == pvr_value */
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unsigned int pvr_mask;
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unsigned int pvr_value;
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char *cpu_name;
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unsigned long cpu_features; /* Kernel features */
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unsigned int cpu_user_features; /* Userland features */
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/* cache line sizes */
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unsigned int icache_bsize;
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unsigned int dcache_bsize;
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/* number of performance monitor counters */
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unsigned int num_pmcs;
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/* this is called to initialize various CPU bits like L1 cache,
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* BHT, SPD, etc... from head.S before branching to identify_machine
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*/
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cpu_setup_t cpu_setup;
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/* Used by oprofile userspace to select the right counters */
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char *oprofile_cpu_type;
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};
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extern struct cpu_spec cpu_specs[];
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extern struct cpu_spec *cur_cpu_spec;
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static inline unsigned long cpu_has_feature(unsigned long feature)
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{
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return cur_cpu_spec->cpu_features & feature;
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}
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#endif /* __ASSEMBLY__ */
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/* CPU kernel features */
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/* Retain the 32b definitions for the time being - use bottom half of word */
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#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
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#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
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#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
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#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
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#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
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#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
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#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
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#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
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#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
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#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
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#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
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#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
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#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
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#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
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#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
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/* Add the 64b processor unique features in the top half of the word */
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#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
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#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
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#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
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#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
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#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
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#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
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#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
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/* unused ASM_CONST(0x0000008000000000) */
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#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
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#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
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#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
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#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
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#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
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#ifndef __ASSEMBLY__
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#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
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PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
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#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
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CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
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CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
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/* iSeries doesn't support large pages */
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#ifdef CONFIG_PPC_ISERIES
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#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
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#else
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#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
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#endif /* CONFIG_PPC_ISERIES */
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#endif /* __ASSEMBLY */
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#ifdef __ASSEMBLY__
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#define BEGIN_FTR_SECTION 98:
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#define END_FTR_SECTION(msk, val) \
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99: \
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.section __ftr_fixup,"a"; \
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.align 3; \
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.llong msk; \
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.llong val; \
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.llong 98b; \
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.llong 99b; \
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.previous
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#else
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#define BEGIN_FTR_SECTION "98:\n"
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#define END_FTR_SECTION(msk, val) \
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"99:\n" \
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" .section __ftr_fixup,\"a\";\n" \
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" .align 3;\n" \
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" .llong "#msk";\n" \
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" .llong "#val";\n" \
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" .llong 98b;\n" \
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" .llong 99b;\n" \
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" .previous\n"
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#endif /* __ASSEMBLY__ */
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#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
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#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
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#endif /* __ASM_PPC_CPUTABLE_H */
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#endif /* __KERNEL__ */
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