26ef5c0957
The ppc32 and ppc64 versions of cacheflush.h were almost identical. The two versions of cache.h are fairly similar, except for a bunch of register definitions in the ppc32 version which probably belong better elsewhere. This patch, therefore, merges both headers. Notable points: - there are several functions in cacheflush.h which exist only on ppc32 or only on ppc64. These are handled by #ifdef for now, but these should probably be consolidated, along with the actual code behind them later. - Confusingly, both ppc32 and ppc64 have a flush_dcache_range(), but they're subtly different: it uses dcbf on ppc32 and dcbst on ppc64, ppc64 has a flush_inval_dcache_range() which uses dcbf. These too should be merged and consolidated later. - Also flush_dcache_range() was defined in cacheflush.h on ppc64, and in cache.h on ppc32. In the merged version it's in cacheflush.h - On ppc32 flush_icache_range() is a normal function from misc.S. On ppc64, it was wrapper, testing a feature bit before calling __flush_icache_range() which does the actual flush. This patch takes the ppc64 approach, which amounts to no change on ppc32, since CPU_FTR_COHERENT_ICACHE will never be set there, but does mean renaming flush_icache_range() to __flush_icache_range() in arch/ppc/kernel/misc.S and arch/powerpc/kernel/misc_32.S - The PReP register info from asm-ppc/cache.h has moved to arch/ppc/platforms/prep_setup.c - The 8xx register info from asm-ppc/cache.h has moved to a new asm-powerpc/reg_8xx.h, included from reg.h - flush_dcache_all() was defined on ppc32 (only), but was never called (although it was exported). Thus this patch removes it from cacheflush.h and from ARCH=powerpc (misc_32.S) entirely. It's left in ARCH=ppc for now, with the prototype moved to ppc_ksyms.c. Built for Walnut (ARCH=ppc), 32-bit multiplatform (pmac, CHRP and PReP ARCH=ppc, pmac and CHRP ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built for 32-bit powermac (ARCH=ppc and ARCH=powerpc). Built and booted on POWER5 LPAR (ARCH=powerpc and ARCH=ppc64). Built and booted on G5 (ARCH=powerpc) Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
41 lines
1011 B
C
41 lines
1011 B
C
#ifndef _ASM_POWERPC_CACHE_H
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#define _ASM_POWERPC_CACHE_H
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#ifdef __KERNEL__
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#include <linux/config.h>
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/* bytes per L1 cache line */
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#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
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#define L1_CACHE_SHIFT 4
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#define MAX_COPY_PREFETCH 1
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#elif defined(CONFIG_PPC32)
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#define L1_CACHE_SHIFT 5
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#define MAX_COPY_PREFETCH 4
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#else /* CONFIG_PPC64 */
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#define L1_CACHE_SHIFT 7
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#endif
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#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
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#define SMP_CACHE_BYTES L1_CACHE_BYTES
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#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
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#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
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struct ppc64_caches {
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u32 dsize; /* L1 d-cache size */
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u32 dline_size; /* L1 d-cache line size */
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u32 log_dline_size;
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u32 dlines_per_page;
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u32 isize; /* L1 i-cache size */
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u32 iline_size; /* L1 i-cache line size */
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u32 log_iline_size;
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u32 ilines_per_page;
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};
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extern struct ppc64_caches ppc64_caches;
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#endif /* __powerpc64__ && ! __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_CACHE_H */
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