16b040129e
Since OMAP4 is using an absolute address, the current PRM accessors are not useable. OMAP4 adaptation for these API are currently ongoing, so define temp version until the proper ones are defined. Signed-off-by: Benoit Cousson <b-cousson@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com> Tested-by: Kevin Hilman <khilman@deeprootsystems.com>
619 lines
20 KiB
C
619 lines
20 KiB
C
/*
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* linux/arch/arm/mach-omap2/prcm.c
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*
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* OMAP 24xx Power Reset and Clock Management (PRCM) functions
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*
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* Copyright (C) 2005 Nokia Corporation
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*
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* Written by Tony Lindgren <tony.lindgren@nokia.com>
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Rajendra Nayak <rnayak@ti.com>
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*
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* Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
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* Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <plat/common.h>
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#include <plat/prcm.h>
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#include <plat/irqs.h>
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#include <plat/control.h>
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#include "clock.h"
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#include "clock2xxx.h"
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#include "cm.h"
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#include "prm.h"
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#include "prm-regbits-24xx.h"
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#include "prm-regbits-44xx.h"
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static void __iomem *prm_base;
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static void __iomem *cm_base;
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static void __iomem *cm2_base;
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#define MAX_MODULE_ENABLE_WAIT 100000
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struct omap3_prcm_regs {
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u32 control_padconf_sys_nirq;
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u32 iva2_cm_clksel1;
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u32 iva2_cm_clksel2;
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u32 cm_sysconfig;
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u32 sgx_cm_clksel;
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u32 dss_cm_clksel;
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u32 cam_cm_clksel;
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u32 per_cm_clksel;
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u32 emu_cm_clksel;
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u32 emu_cm_clkstctrl;
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u32 pll_cm_autoidle2;
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u32 pll_cm_clksel4;
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u32 pll_cm_clksel5;
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u32 pll_cm_clken2;
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u32 cm_polctrl;
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u32 iva2_cm_fclken;
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u32 iva2_cm_clken_pll;
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u32 core_cm_fclken1;
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u32 core_cm_fclken3;
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u32 sgx_cm_fclken;
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u32 wkup_cm_fclken;
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u32 dss_cm_fclken;
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u32 cam_cm_fclken;
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u32 per_cm_fclken;
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u32 usbhost_cm_fclken;
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u32 core_cm_iclken1;
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u32 core_cm_iclken2;
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u32 core_cm_iclken3;
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u32 sgx_cm_iclken;
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u32 wkup_cm_iclken;
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u32 dss_cm_iclken;
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u32 cam_cm_iclken;
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u32 per_cm_iclken;
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u32 usbhost_cm_iclken;
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u32 iva2_cm_autiidle2;
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u32 mpu_cm_autoidle2;
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u32 iva2_cm_clkstctrl;
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u32 mpu_cm_clkstctrl;
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u32 core_cm_clkstctrl;
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u32 sgx_cm_clkstctrl;
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u32 dss_cm_clkstctrl;
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u32 cam_cm_clkstctrl;
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u32 per_cm_clkstctrl;
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u32 neon_cm_clkstctrl;
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u32 usbhost_cm_clkstctrl;
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u32 core_cm_autoidle1;
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u32 core_cm_autoidle2;
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u32 core_cm_autoidle3;
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u32 wkup_cm_autoidle;
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u32 dss_cm_autoidle;
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u32 cam_cm_autoidle;
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u32 per_cm_autoidle;
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u32 usbhost_cm_autoidle;
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u32 sgx_cm_sleepdep;
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u32 dss_cm_sleepdep;
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u32 cam_cm_sleepdep;
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u32 per_cm_sleepdep;
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u32 usbhost_cm_sleepdep;
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u32 cm_clkout_ctrl;
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u32 prm_clkout_ctrl;
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u32 sgx_pm_wkdep;
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u32 dss_pm_wkdep;
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u32 cam_pm_wkdep;
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u32 per_pm_wkdep;
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u32 neon_pm_wkdep;
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u32 usbhost_pm_wkdep;
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u32 core_pm_mpugrpsel1;
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u32 iva2_pm_ivagrpsel1;
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u32 core_pm_mpugrpsel3;
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u32 core_pm_ivagrpsel3;
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u32 wkup_pm_mpugrpsel;
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u32 wkup_pm_ivagrpsel;
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u32 per_pm_mpugrpsel;
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u32 per_pm_ivagrpsel;
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u32 wkup_pm_wken;
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};
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struct omap3_prcm_regs prcm_context;
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u32 omap_prcm_get_reset_sources(void)
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{
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/* XXX This presumably needs modification for 34XX */
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if (cpu_is_omap24xx() || cpu_is_omap34xx())
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return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f;
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if (cpu_is_omap44xx())
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return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f;
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return 0;
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}
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EXPORT_SYMBOL(omap_prcm_get_reset_sources);
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/* Resets clock rates and reboots the system. Only called from system.h */
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void omap_prcm_arch_reset(char mode, const char *cmd)
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{
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s16 prcm_offs = 0;
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if (cpu_is_omap24xx()) {
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omap2xxx_clk_prepare_for_reboot();
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prcm_offs = WKUP_MOD;
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} else if (cpu_is_omap34xx()) {
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u32 l;
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prcm_offs = OMAP3430_GR_MOD;
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l = ('B' << 24) | ('M' << 16) | (cmd ? (u8)*cmd : 0);
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/* Reserve the first word in scratchpad for communicating
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* with the boot ROM. A pointer to a data structure
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* describing the boot process can be stored there,
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* cf. OMAP34xx TRM, Initialization / Software Booting
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* Configuration. */
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omap_writel(l, OMAP343X_SCRATCHPAD + 4);
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} else if (cpu_is_omap44xx())
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prcm_offs = OMAP4430_PRM_DEVICE_MOD;
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else
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WARN_ON(1);
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if (cpu_is_omap24xx() || cpu_is_omap34xx())
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prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs,
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OMAP2_RM_RSTCTRL);
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if (cpu_is_omap44xx())
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prm_set_mod_reg_bits(OMAP4430_RST_GLOBAL_WARM_SW_MASK,
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prcm_offs, OMAP4_RM_RSTCTRL);
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}
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static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg)
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{
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BUG_ON(!base);
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return __raw_readl(base + module + reg);
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}
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static inline void __omap_prcm_write(u32 value, void __iomem *base,
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s16 module, u16 reg)
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{
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BUG_ON(!base);
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__raw_writel(value, base + module + reg);
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}
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/* Read a register in a PRM module */
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u32 prm_read_mod_reg(s16 module, u16 idx)
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{
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return __omap_prcm_read(prm_base, module, idx);
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}
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/* Write into a register in a PRM module */
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void prm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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__omap_prcm_write(val, prm_base, module, idx);
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}
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/* Read-modify-write a register in a PRM module. Caller must lock */
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u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
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{
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u32 v;
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v = prm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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prm_write_mod_reg(v, module, idx);
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return v;
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}
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/* Read a PRM register, AND it, and shift the result down to bit 0 */
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u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask)
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{
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u32 v;
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v = prm_read_mod_reg(domain, idx);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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/* Read a PRM register, AND it, and shift the result down to bit 0 */
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u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
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{
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u32 v;
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v = __raw_readl(reg);
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v &= mask;
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v >>= __ffs(mask);
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return v;
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}
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/* Read-modify-write a register in a PRM module. Caller must lock */
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u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
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{
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u32 v;
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v = __raw_readl(reg);
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v &= ~mask;
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v |= bits;
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__raw_writel(v, reg);
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return v;
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}
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/* Read a register in a CM module */
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u32 cm_read_mod_reg(s16 module, u16 idx)
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{
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return __omap_prcm_read(cm_base, module, idx);
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}
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/* Write into a register in a CM module */
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void cm_write_mod_reg(u32 val, s16 module, u16 idx)
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{
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__omap_prcm_write(val, cm_base, module, idx);
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}
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/* Read-modify-write a register in a CM module. Caller must lock */
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u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx)
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{
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u32 v;
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v = cm_read_mod_reg(module, idx);
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v &= ~mask;
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v |= bits;
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cm_write_mod_reg(v, module, idx);
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return v;
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}
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/**
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* omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
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* @reg: physical address of module IDLEST register
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* @mask: value to mask against to determine if the module is active
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* @idlest: idle state indicator (0 or 1) for the clock
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* @name: name of the clock (for printk)
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*
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* Returns 1 if the module indicated readiness in time, or 0 if it
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* failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
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*/
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int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest,
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const char *name)
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{
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int i = 0;
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int ena = 0;
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if (idlest)
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ena = 0;
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else
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ena = mask;
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/* Wait for lock */
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omap_test_timeout(((__raw_readl(reg) & mask) == ena),
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MAX_MODULE_ENABLE_WAIT, i);
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if (i < MAX_MODULE_ENABLE_WAIT)
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pr_debug("cm: Module associated with clock %s ready after %d "
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"loops\n", name, i);
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else
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pr_err("cm: Module associated with clock %s didn't enable in "
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"%d tries\n", name, MAX_MODULE_ENABLE_WAIT);
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return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
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};
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void __init omap2_set_globals_prcm(struct omap_globals *omap2_globals)
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{
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/* Static mapping, never released */
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if (omap2_globals->prm) {
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prm_base = ioremap(omap2_globals->prm, SZ_8K);
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WARN_ON(!prm_base);
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}
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if (omap2_globals->cm) {
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cm_base = ioremap(omap2_globals->cm, SZ_8K);
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WARN_ON(!cm_base);
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}
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if (omap2_globals->cm2) {
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cm2_base = ioremap(omap2_globals->cm2, SZ_8K);
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WARN_ON(!cm2_base);
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}
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}
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#ifdef CONFIG_ARCH_OMAP3
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void omap3_prcm_save_context(void)
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{
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prcm_context.control_padconf_sys_nirq =
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omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ);
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prcm_context.iva2_cm_clksel1 =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1);
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prcm_context.iva2_cm_clksel2 =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2);
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prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG);
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prcm_context.sgx_cm_clksel =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL);
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prcm_context.dss_cm_clksel =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL);
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prcm_context.cam_cm_clksel =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL);
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prcm_context.per_cm_clksel =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL);
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prcm_context.emu_cm_clksel =
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cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1);
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prcm_context.emu_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.pll_cm_autoidle2 =
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cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2);
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prcm_context.pll_cm_clksel4 =
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cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4);
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prcm_context.pll_cm_clksel5 =
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cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5);
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prcm_context.pll_cm_clken2 =
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cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2);
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prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL);
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prcm_context.iva2_cm_fclken =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN);
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prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD,
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OMAP3430_CM_CLKEN_PLL);
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prcm_context.core_cm_fclken1 =
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cm_read_mod_reg(CORE_MOD, CM_FCLKEN1);
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prcm_context.core_cm_fclken3 =
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cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3);
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prcm_context.sgx_cm_fclken =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN);
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prcm_context.wkup_cm_fclken =
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cm_read_mod_reg(WKUP_MOD, CM_FCLKEN);
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prcm_context.dss_cm_fclken =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN);
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prcm_context.cam_cm_fclken =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN);
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prcm_context.per_cm_fclken =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN);
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prcm_context.usbhost_cm_fclken =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
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prcm_context.core_cm_iclken1 =
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cm_read_mod_reg(CORE_MOD, CM_ICLKEN1);
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prcm_context.core_cm_iclken2 =
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cm_read_mod_reg(CORE_MOD, CM_ICLKEN2);
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prcm_context.core_cm_iclken3 =
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cm_read_mod_reg(CORE_MOD, CM_ICLKEN3);
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prcm_context.sgx_cm_iclken =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN);
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prcm_context.wkup_cm_iclken =
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cm_read_mod_reg(WKUP_MOD, CM_ICLKEN);
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prcm_context.dss_cm_iclken =
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cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN);
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prcm_context.cam_cm_iclken =
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cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN);
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prcm_context.per_cm_iclken =
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cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN);
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prcm_context.usbhost_cm_iclken =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
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prcm_context.iva2_cm_autiidle2 =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2);
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prcm_context.mpu_cm_autoidle2 =
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cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2);
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prcm_context.iva2_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.mpu_cm_clkstctrl =
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cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.core_cm_clkstctrl =
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cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.sgx_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430ES2_SGX_MOD,
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OMAP2_CM_CLKSTCTRL);
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prcm_context.dss_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.cam_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.per_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.neon_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL);
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prcm_context.usbhost_cm_clkstctrl =
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cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD,
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OMAP2_CM_CLKSTCTRL);
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prcm_context.core_cm_autoidle1 =
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cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1);
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prcm_context.core_cm_autoidle2 =
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cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2);
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prcm_context.core_cm_autoidle3 =
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cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3);
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prcm_context.wkup_cm_autoidle =
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cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE);
|
|
prcm_context.dss_cm_autoidle =
|
|
cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE);
|
|
prcm_context.cam_cm_autoidle =
|
|
cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE);
|
|
prcm_context.per_cm_autoidle =
|
|
cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
|
|
prcm_context.usbhost_cm_autoidle =
|
|
cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
|
|
prcm_context.sgx_cm_sleepdep =
|
|
cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP);
|
|
prcm_context.dss_cm_sleepdep =
|
|
cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP);
|
|
prcm_context.cam_cm_sleepdep =
|
|
cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP);
|
|
prcm_context.per_cm_sleepdep =
|
|
cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP);
|
|
prcm_context.usbhost_cm_sleepdep =
|
|
cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
|
|
prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD,
|
|
OMAP3_CM_CLKOUT_CTRL_OFFSET);
|
|
prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD,
|
|
OMAP3_PRM_CLKOUT_CTRL_OFFSET);
|
|
prcm_context.sgx_pm_wkdep =
|
|
prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP);
|
|
prcm_context.dss_pm_wkdep =
|
|
prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP);
|
|
prcm_context.cam_pm_wkdep =
|
|
prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP);
|
|
prcm_context.per_pm_wkdep =
|
|
prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP);
|
|
prcm_context.neon_pm_wkdep =
|
|
prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP);
|
|
prcm_context.usbhost_pm_wkdep =
|
|
prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
|
|
prcm_context.core_pm_mpugrpsel1 =
|
|
prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1);
|
|
prcm_context.iva2_pm_ivagrpsel1 =
|
|
prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1);
|
|
prcm_context.core_pm_mpugrpsel3 =
|
|
prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3);
|
|
prcm_context.core_pm_ivagrpsel3 =
|
|
prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
|
|
prcm_context.wkup_pm_mpugrpsel =
|
|
prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
prcm_context.wkup_pm_ivagrpsel =
|
|
prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
prcm_context.per_pm_mpugrpsel =
|
|
prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);
|
|
prcm_context.per_pm_ivagrpsel =
|
|
prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
|
|
prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN);
|
|
return;
|
|
}
|
|
|
|
void omap3_prcm_restore_context(void)
|
|
{
|
|
omap_ctrl_writel(prcm_context.control_padconf_sys_nirq,
|
|
OMAP343X_CONTROL_PADCONF_SYSNIRQ);
|
|
cm_write_mod_reg(prcm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD,
|
|
CM_CLKSEL1);
|
|
cm_write_mod_reg(prcm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD,
|
|
CM_CLKSEL2);
|
|
__raw_writel(prcm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG);
|
|
cm_write_mod_reg(prcm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD,
|
|
CM_CLKSEL);
|
|
cm_write_mod_reg(prcm_context.dss_cm_clksel, OMAP3430_DSS_MOD,
|
|
CM_CLKSEL);
|
|
cm_write_mod_reg(prcm_context.cam_cm_clksel, OMAP3430_CAM_MOD,
|
|
CM_CLKSEL);
|
|
cm_write_mod_reg(prcm_context.per_cm_clksel, OMAP3430_PER_MOD,
|
|
CM_CLKSEL);
|
|
cm_write_mod_reg(prcm_context.emu_cm_clksel, OMAP3430_EMU_MOD,
|
|
CM_CLKSEL1);
|
|
cm_write_mod_reg(prcm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.pll_cm_autoidle2, PLL_MOD,
|
|
CM_AUTOIDLE2);
|
|
cm_write_mod_reg(prcm_context.pll_cm_clksel4, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKSEL4);
|
|
cm_write_mod_reg(prcm_context.pll_cm_clksel5, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKSEL5);
|
|
cm_write_mod_reg(prcm_context.pll_cm_clken2, PLL_MOD,
|
|
OMAP3430ES2_CM_CLKEN2);
|
|
__raw_writel(prcm_context.cm_polctrl, OMAP3430_CM_POLCTRL);
|
|
cm_write_mod_reg(prcm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD,
|
|
CM_FCLKEN);
|
|
cm_write_mod_reg(prcm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD,
|
|
OMAP3430_CM_CLKEN_PLL);
|
|
cm_write_mod_reg(prcm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1);
|
|
cm_write_mod_reg(prcm_context.core_cm_fclken3, CORE_MOD,
|
|
OMAP3430ES2_CM_FCLKEN3);
|
|
cm_write_mod_reg(prcm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD,
|
|
CM_FCLKEN);
|
|
cm_write_mod_reg(prcm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN);
|
|
cm_write_mod_reg(prcm_context.dss_cm_fclken, OMAP3430_DSS_MOD,
|
|
CM_FCLKEN);
|
|
cm_write_mod_reg(prcm_context.cam_cm_fclken, OMAP3430_CAM_MOD,
|
|
CM_FCLKEN);
|
|
cm_write_mod_reg(prcm_context.per_cm_fclken, OMAP3430_PER_MOD,
|
|
CM_FCLKEN);
|
|
cm_write_mod_reg(prcm_context.usbhost_cm_fclken,
|
|
OMAP3430ES2_USBHOST_MOD, CM_FCLKEN);
|
|
cm_write_mod_reg(prcm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1);
|
|
cm_write_mod_reg(prcm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2);
|
|
cm_write_mod_reg(prcm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3);
|
|
cm_write_mod_reg(prcm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD,
|
|
CM_ICLKEN);
|
|
cm_write_mod_reg(prcm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN);
|
|
cm_write_mod_reg(prcm_context.dss_cm_iclken, OMAP3430_DSS_MOD,
|
|
CM_ICLKEN);
|
|
cm_write_mod_reg(prcm_context.cam_cm_iclken, OMAP3430_CAM_MOD,
|
|
CM_ICLKEN);
|
|
cm_write_mod_reg(prcm_context.per_cm_iclken, OMAP3430_PER_MOD,
|
|
CM_ICLKEN);
|
|
cm_write_mod_reg(prcm_context.usbhost_cm_iclken,
|
|
OMAP3430ES2_USBHOST_MOD, CM_ICLKEN);
|
|
cm_write_mod_reg(prcm_context.iva2_cm_autiidle2, OMAP3430_IVA2_MOD,
|
|
CM_AUTOIDLE2);
|
|
cm_write_mod_reg(prcm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2);
|
|
cm_write_mod_reg(prcm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.mpu_cm_clkstctrl, MPU_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.core_cm_clkstctrl, CORE_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.per_cm_clkstctrl, OMAP3430_PER_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD,
|
|
OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.usbhost_cm_clkstctrl,
|
|
OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL);
|
|
cm_write_mod_reg(prcm_context.core_cm_autoidle1, CORE_MOD,
|
|
CM_AUTOIDLE1);
|
|
cm_write_mod_reg(prcm_context.core_cm_autoidle2, CORE_MOD,
|
|
CM_AUTOIDLE2);
|
|
cm_write_mod_reg(prcm_context.core_cm_autoidle3, CORE_MOD,
|
|
CM_AUTOIDLE3);
|
|
cm_write_mod_reg(prcm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE);
|
|
cm_write_mod_reg(prcm_context.dss_cm_autoidle, OMAP3430_DSS_MOD,
|
|
CM_AUTOIDLE);
|
|
cm_write_mod_reg(prcm_context.cam_cm_autoidle, OMAP3430_CAM_MOD,
|
|
CM_AUTOIDLE);
|
|
cm_write_mod_reg(prcm_context.per_cm_autoidle, OMAP3430_PER_MOD,
|
|
CM_AUTOIDLE);
|
|
cm_write_mod_reg(prcm_context.usbhost_cm_autoidle,
|
|
OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE);
|
|
cm_write_mod_reg(prcm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_write_mod_reg(prcm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_write_mod_reg(prcm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_write_mod_reg(prcm_context.per_cm_sleepdep, OMAP3430_PER_MOD,
|
|
OMAP3430_CM_SLEEPDEP);
|
|
cm_write_mod_reg(prcm_context.usbhost_cm_sleepdep,
|
|
OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP);
|
|
cm_write_mod_reg(prcm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD,
|
|
OMAP3_CM_CLKOUT_CTRL_OFFSET);
|
|
prm_write_mod_reg(prcm_context.prm_clkout_ctrl, OMAP3430_CCR_MOD,
|
|
OMAP3_PRM_CLKOUT_CTRL_OFFSET);
|
|
prm_write_mod_reg(prcm_context.sgx_pm_wkdep, OMAP3430ES2_SGX_MOD,
|
|
PM_WKDEP);
|
|
prm_write_mod_reg(prcm_context.dss_pm_wkdep, OMAP3430_DSS_MOD,
|
|
PM_WKDEP);
|
|
prm_write_mod_reg(prcm_context.cam_pm_wkdep, OMAP3430_CAM_MOD,
|
|
PM_WKDEP);
|
|
prm_write_mod_reg(prcm_context.per_pm_wkdep, OMAP3430_PER_MOD,
|
|
PM_WKDEP);
|
|
prm_write_mod_reg(prcm_context.neon_pm_wkdep, OMAP3430_NEON_MOD,
|
|
PM_WKDEP);
|
|
prm_write_mod_reg(prcm_context.usbhost_pm_wkdep,
|
|
OMAP3430ES2_USBHOST_MOD, PM_WKDEP);
|
|
prm_write_mod_reg(prcm_context.core_pm_mpugrpsel1, CORE_MOD,
|
|
OMAP3430_PM_MPUGRPSEL1);
|
|
prm_write_mod_reg(prcm_context.iva2_pm_ivagrpsel1, OMAP3430_IVA2_MOD,
|
|
OMAP3430_PM_IVAGRPSEL1);
|
|
prm_write_mod_reg(prcm_context.core_pm_mpugrpsel3, CORE_MOD,
|
|
OMAP3430ES2_PM_MPUGRPSEL3);
|
|
prm_write_mod_reg(prcm_context.core_pm_ivagrpsel3, CORE_MOD,
|
|
OMAP3430ES2_PM_IVAGRPSEL3);
|
|
prm_write_mod_reg(prcm_context.wkup_pm_mpugrpsel, WKUP_MOD,
|
|
OMAP3430_PM_MPUGRPSEL);
|
|
prm_write_mod_reg(prcm_context.wkup_pm_ivagrpsel, WKUP_MOD,
|
|
OMAP3430_PM_IVAGRPSEL);
|
|
prm_write_mod_reg(prcm_context.per_pm_mpugrpsel, OMAP3430_PER_MOD,
|
|
OMAP3430_PM_MPUGRPSEL);
|
|
prm_write_mod_reg(prcm_context.per_pm_ivagrpsel, OMAP3430_PER_MOD,
|
|
OMAP3430_PM_IVAGRPSEL);
|
|
prm_write_mod_reg(prcm_context.wkup_pm_wken, WKUP_MOD, PM_WKEN);
|
|
return;
|
|
}
|
|
#endif
|