5f15fbb68f
This is the hw module for DM644x CCDC. This registers with the vpfe capture driver and provides a set of hw_ops to configure CCDC for a specific decoder device connected to the VPFE. Reviewed by: Hans Verkuil <hverkuil@xs4all.nl> Reviewed by: Laurent Pinchart <laurent.pinchart@skynet.be> Signed-off-by: Muralidharan Karicheri <m-karicheri2@ti.com> Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
146 lines
5.1 KiB
C
146 lines
5.1 KiB
C
/*
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* Copyright (C) 2006-2009 Texas Instruments Inc
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _DM644X_CCDC_REGS_H
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#define _DM644X_CCDC_REGS_H
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/**************************************************************************\
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* Register OFFSET Definitions
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\**************************************************************************/
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#define CCDC_PID 0x0
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#define CCDC_PCR 0x4
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#define CCDC_SYN_MODE 0x8
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#define CCDC_HD_VD_WID 0xc
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#define CCDC_PIX_LINES 0x10
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#define CCDC_HORZ_INFO 0x14
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#define CCDC_VERT_START 0x18
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#define CCDC_VERT_LINES 0x1c
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#define CCDC_CULLING 0x20
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#define CCDC_HSIZE_OFF 0x24
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#define CCDC_SDOFST 0x28
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#define CCDC_SDR_ADDR 0x2c
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#define CCDC_CLAMP 0x30
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#define CCDC_DCSUB 0x34
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#define CCDC_COLPTN 0x38
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#define CCDC_BLKCMP 0x3c
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#define CCDC_FPC 0x40
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#define CCDC_FPC_ADDR 0x44
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#define CCDC_VDINT 0x48
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#define CCDC_ALAW 0x4c
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#define CCDC_REC656IF 0x50
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#define CCDC_CCDCFG 0x54
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#define CCDC_FMTCFG 0x58
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#define CCDC_FMT_HORZ 0x5c
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#define CCDC_FMT_VERT 0x60
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#define CCDC_FMT_ADDR0 0x64
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#define CCDC_FMT_ADDR1 0x68
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#define CCDC_FMT_ADDR2 0x6c
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#define CCDC_FMT_ADDR3 0x70
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#define CCDC_FMT_ADDR4 0x74
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#define CCDC_FMT_ADDR5 0x78
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#define CCDC_FMT_ADDR6 0x7c
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#define CCDC_FMT_ADDR7 0x80
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#define CCDC_PRGEVEN_0 0x84
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#define CCDC_PRGEVEN_1 0x88
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#define CCDC_PRGODD_0 0x8c
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#define CCDC_PRGODD_1 0x90
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#define CCDC_VP_OUT 0x94
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/***************************************************************
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* Define for various register bit mask and shifts for CCDC
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****************************************************************/
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#define CCDC_FID_POL_MASK 1
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#define CCDC_FID_POL_SHIFT 4
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#define CCDC_HD_POL_MASK 1
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#define CCDC_HD_POL_SHIFT 3
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#define CCDC_VD_POL_MASK 1
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#define CCDC_VD_POL_SHIFT 2
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#define CCDC_HSIZE_OFF_MASK 0xffffffe0
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#define CCDC_32BYTE_ALIGN_VAL 31
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#define CCDC_FRM_FMT_MASK 0x1
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#define CCDC_FRM_FMT_SHIFT 7
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#define CCDC_DATA_SZ_MASK 7
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#define CCDC_DATA_SZ_SHIFT 8
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#define CCDC_PIX_FMT_MASK 3
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#define CCDC_PIX_FMT_SHIFT 12
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#define CCDC_VP2SDR_DISABLE 0xFFFBFFFF
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#define CCDC_WEN_ENABLE (1 << 17)
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#define CCDC_SDR2RSZ_DISABLE 0xFFF7FFFF
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#define CCDC_VDHDEN_ENABLE (1 << 16)
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#define CCDC_LPF_ENABLE (1 << 14)
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#define CCDC_ALAW_ENABLE (1 << 3)
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#define CCDC_ALAW_GAMA_WD_MASK 7
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#define CCDC_BLK_CLAMP_ENABLE (1 << 31)
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#define CCDC_BLK_SGAIN_MASK 0x1F
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#define CCDC_BLK_ST_PXL_MASK 0x7FFF
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#define CCDC_BLK_ST_PXL_SHIFT 10
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#define CCDC_BLK_SAMPLE_LN_MASK 7
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#define CCDC_BLK_SAMPLE_LN_SHIFT 28
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#define CCDC_BLK_SAMPLE_LINE_MASK 7
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#define CCDC_BLK_SAMPLE_LINE_SHIFT 25
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#define CCDC_BLK_DC_SUB_MASK 0x03FFF
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#define CCDC_BLK_COMP_MASK 0xFF
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#define CCDC_BLK_COMP_GB_COMP_SHIFT 8
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#define CCDC_BLK_COMP_GR_COMP_SHIFT 16
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#define CCDC_BLK_COMP_R_COMP_SHIFT 24
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#define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15)
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#define CCDC_FPC_ENABLE (1 << 15)
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#define CCDC_FPC_DISABLE 0
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#define CCDC_FPC_FPC_NUM_MASK 0x7FFF
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#define CCDC_DATA_PACK_ENABLE (1 << 11)
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#define CCDC_FMTCFG_VPIN_MASK 7
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#define CCDC_FMTCFG_VPIN_SHIFT 12
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#define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF
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#define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF
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#define CCDC_FMT_HORZ_FMTSPH_SHIFT 16
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#define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF
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#define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF
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#define CCDC_FMT_VERT_FMTSLV_SHIFT 16
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#define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF
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#define CCDC_VP_OUT_VERT_NUM_SHIFT 17
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#define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF
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#define CCDC_VP_OUT_HORZ_NUM_SHIFT 4
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#define CCDC_VP_OUT_HORZ_ST_MASK 0xF
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#define CCDC_HORZ_INFO_SPH_SHIFT 16
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#define CCDC_VERT_START_SLV0_SHIFT 16
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#define CCDC_VDINT_VDINT0_SHIFT 16
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#define CCDC_VDINT_VDINT1_MASK 0xFFFF
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#define CCDC_PPC_RAW 1
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#define CCDC_DCSUB_DEFAULT_VAL 0
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#define CCDC_CLAMP_DEFAULT_VAL 0
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#define CCDC_ENABLE_VIDEO_PORT 0x8000
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#define CCDC_DISABLE_VIDEO_PORT 0
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#define CCDC_COLPTN_VAL 0xBB11BB11
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#define CCDC_TWO_BYTES_PER_PIXEL 2
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#define CCDC_INTERLACED_IMAGE_INVERT 0x4B6D
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#define CCDC_INTERLACED_NO_IMAGE_INVERT 0x0249
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#define CCDC_PROGRESSIVE_IMAGE_INVERT 0x4000
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#define CCDC_PROGRESSIVE_NO_IMAGE_INVERT 0
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#define CCDC_INTERLACED_HEIGHT_SHIFT 1
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#define CCDC_SYN_MODE_INPMOD_SHIFT 12
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#define CCDC_SYN_MODE_INPMOD_MASK 3
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#define CCDC_SYN_MODE_8BITS (7 << 8)
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#define CCDC_SYN_FLDMODE_MASK 1
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#define CCDC_SYN_FLDMODE_SHIFT 7
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#define CCDC_REC656IF_BT656_EN 3
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#define CCDC_SYN_MODE_VD_POL_NEGATIVE (1 << 2)
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#define CCDC_CCDCFG_Y8POS_SHIFT 11
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#define CCDC_SDOFST_FIELD_INTERLEAVED 0x249
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#define CCDC_NO_CULLING 0xffff00ff
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#endif
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