d37ea5d562
This implements the core new functions needed for ich8's internal NIC. This includes: * ich8 specific read/write code * flash/nvm access code * software semaphore flag functions * 10/100 PHY (fe - no gigabit speed) support for low-end versions * A workaround for a powerdown sequence problem discovered that affects a small number of motherboard. Signed-off-by: Jesse Brandeburg <jesse.brandeburg@intel.com> Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com>
144 lines
4.5 KiB
C
144 lines
4.5 KiB
C
/*******************************************************************************
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Copyright(c) 1999 - 2006 Intel Corporation. All rights reserved.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59
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Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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The full GNU General Public License is included in this distribution in the
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file called LICENSE.
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* glue for the OS independent part of e1000
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* includes register access macros
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*/
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#ifndef _E1000_OSDEP_H_
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#define _E1000_OSDEP_H_
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <asm/io.h>
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#include <linux/interrupt.h>
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#include <linux/sched.h>
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#ifndef msec_delay
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#define msec_delay(x) do { if(in_interrupt()) { \
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/* Don't mdelay in interrupt context! */ \
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BUG(); \
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} else { \
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msleep(x); \
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} } while (0)
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/* Some workarounds require millisecond delays and are run during interrupt
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* context. Most notably, when establishing link, the phy may need tweaking
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* but cannot process phy register reads/writes faster than millisecond
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* intervals...and we establish link due to a "link status change" interrupt.
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*/
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#define msec_delay_irq(x) mdelay(x)
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#endif
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#define PCI_COMMAND_REGISTER PCI_COMMAND
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#define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
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typedef enum {
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#undef FALSE
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FALSE = 0,
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#undef TRUE
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TRUE = 1
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} boolean_t;
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#define MSGOUT(S, A, B) printk(KERN_DEBUG S "\n", A, B)
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#ifdef DBG
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#define DEBUGOUT(S) printk(KERN_DEBUG S "\n")
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#define DEBUGOUT1(S, A...) printk(KERN_DEBUG S "\n", A)
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#else
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#define DEBUGOUT(S)
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#define DEBUGOUT1(S, A...)
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#endif
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#define DEBUGFUNC(F) DEBUGOUT(F)
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#define DEBUGOUT2 DEBUGOUT1
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#define DEBUGOUT3 DEBUGOUT2
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#define DEBUGOUT7 DEBUGOUT3
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#define E1000_WRITE_REG(a, reg, value) ( \
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writel((value), ((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg))))
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#define E1000_READ_REG(a, reg) ( \
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readl((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg)))
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#define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
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writel((value), ((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
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((offset) << 2))))
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#define E1000_READ_REG_ARRAY(a, reg, offset) ( \
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readl((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
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((offset) << 2)))
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#define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
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#define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
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#define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
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writew((value), ((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
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((offset) << 1))))
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#define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
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readw((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
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((offset) << 1)))
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#define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
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writeb((value), ((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
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(offset))))
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#define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
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readb((a)->hw_addr + \
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(((a)->mac_type >= e1000_82543) ? E1000_##reg : E1000_82542_##reg) + \
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(offset)))
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#define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, STATUS)
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#define E1000_WRITE_ICH8_REG(a, reg, value) ( \
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writel((value), ((a)->flash_address + reg)))
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#define E1000_READ_ICH8_REG(a, reg) ( \
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readl((a)->flash_address + reg))
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#define E1000_WRITE_ICH8_REG16(a, reg, value) ( \
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writew((value), ((a)->flash_address + reg)))
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#define E1000_READ_ICH8_REG16(a, reg) ( \
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readw((a)->flash_address + reg))
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#endif /* _E1000_OSDEP_H_ */
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