976119bc5d
Signed-off-by: Graf Yang <graf.yang@analog.com> Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
137 lines
5.0 KiB
C
137 lines
5.0 KiB
C
/*
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* File: include/asm-blackfin/mach-bf518/anomaly.h
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* Bugs: Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (C) 2004-2009 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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/* This file should be up to date with:
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* - Revision C, 06/12/2009; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
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*/
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/* We plan on not supporting 0.0 silicon, but 0.1 isn't out yet - sorry */
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#if __SILICON_REVISION__ < 0
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# error will not work on BF518 silicon version
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#endif
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#ifndef _MACH_ANOMALY_H_
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#define _MACH_ANOMALY_H_
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/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
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#define ANOMALY_05000074 (1)
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/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
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#define ANOMALY_05000122 (1)
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/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
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#define ANOMALY_05000245 (1)
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/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
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#define ANOMALY_05000254 (1)
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/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
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#define ANOMALY_05000265 (1)
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/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
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#define ANOMALY_05000310 (1)
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/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
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#define ANOMALY_05000366 (1)
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/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
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#define ANOMALY_05000405 (1)
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/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
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#define ANOMALY_05000408 (1)
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/* Speculative Fetches Can Cause Undesired External FIFO Operations */
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#define ANOMALY_05000416 (1)
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/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
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#define ANOMALY_05000421 (1)
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/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
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#define ANOMALY_05000422 (1)
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/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
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#define ANOMALY_05000426 (1)
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/* Software System Reset Corrupts PLL_LOCKCNT Register */
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#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
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/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
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#define ANOMALY_05000431 (1)
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/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
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#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
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/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
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#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
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/* Preboot Cannot be Used to Alter the PLL_DIV Register */
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#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
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/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
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#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
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/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
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#define ANOMALY_05000443 (1)
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/* Incorrect L1 Instruction Bank B Memory Map Location */
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#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
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/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
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#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
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/* PWM_TRIPB Signal Not Available on PG10 */
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#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
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/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
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#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
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/* False Hardware Error when RETI Points to Invalid Memory */
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#define ANOMALY_05000461 (1)
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/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
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#define ANOMALY_05000462 (1)
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/* Anomalies that don't exist on this proc */
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#define ANOMALY_05000099 (0)
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#define ANOMALY_05000119 (0)
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#define ANOMALY_05000120 (0)
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#define ANOMALY_05000125 (0)
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#define ANOMALY_05000149 (0)
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#define ANOMALY_05000158 (0)
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#define ANOMALY_05000171 (0)
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#define ANOMALY_05000179 (0)
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#define ANOMALY_05000182 (0)
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#define ANOMALY_05000183 (0)
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#define ANOMALY_05000189 (0)
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#define ANOMALY_05000198 (0)
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#define ANOMALY_05000202 (0)
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#define ANOMALY_05000215 (0)
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#define ANOMALY_05000220 (0)
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#define ANOMALY_05000227 (0)
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#define ANOMALY_05000230 (0)
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#define ANOMALY_05000231 (0)
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#define ANOMALY_05000233 (0)
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#define ANOMALY_05000234 (0)
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#define ANOMALY_05000242 (0)
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#define ANOMALY_05000244 (0)
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#define ANOMALY_05000248 (0)
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#define ANOMALY_05000250 (0)
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#define ANOMALY_05000257 (0)
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#define ANOMALY_05000261 (0)
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#define ANOMALY_05000263 (0)
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#define ANOMALY_05000266 (0)
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#define ANOMALY_05000273 (0)
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#define ANOMALY_05000274 (0)
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#define ANOMALY_05000278 (0)
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#define ANOMALY_05000281 (0)
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#define ANOMALY_05000283 (0)
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#define ANOMALY_05000285 (0)
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#define ANOMALY_05000287 (0)
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#define ANOMALY_05000301 (0)
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#define ANOMALY_05000305 (0)
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#define ANOMALY_05000307 (0)
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#define ANOMALY_05000311 (0)
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#define ANOMALY_05000312 (0)
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#define ANOMALY_05000315 (0)
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#define ANOMALY_05000323 (0)
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#define ANOMALY_05000353 (0)
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#define ANOMALY_05000357 (0)
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#define ANOMALY_05000362 (1)
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#define ANOMALY_05000363 (0)
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#define ANOMALY_05000364 (0)
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#define ANOMALY_05000371 (0)
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#define ANOMALY_05000380 (0)
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#define ANOMALY_05000386 (0)
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#define ANOMALY_05000389 (0)
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#define ANOMALY_05000400 (0)
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#define ANOMALY_05000412 (0)
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#define ANOMALY_05000432 (0)
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#define ANOMALY_05000447 (0)
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#define ANOMALY_05000448 (0)
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#define ANOMALY_05000456 (0)
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#define ANOMALY_05000450 (0)
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#define ANOMALY_05000465 (0)
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#define ANOMALY_05000467 (0)
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#endif
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