0f43563f2d
This patch updates the IRQ combiner chained IRQ handler code to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control. This is required for the GIC to move to fasteoi interrupt handling. Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
125 lines
3.1 KiB
C
125 lines
3.1 KiB
C
/* linux/arch/arm/mach-exynos4/irq-combiner.c
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*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Based on arch/arm/common/gic.c
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*
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* IRQ COMBINER support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#define COMBINER_ENABLE_SET 0x0
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#define COMBINER_ENABLE_CLEAR 0x4
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#define COMBINER_INT_STATUS 0xC
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static DEFINE_SPINLOCK(irq_controller_lock);
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struct combiner_chip_data {
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unsigned int irq_offset;
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unsigned int irq_mask;
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void __iomem *base;
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};
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static struct combiner_chip_data combiner_data[MAX_COMBINER_NR];
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static inline void __iomem *combiner_base(struct irq_data *data)
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{
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struct combiner_chip_data *combiner_data =
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irq_data_get_irq_chip_data(data);
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return combiner_data->base;
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}
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static void combiner_mask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->irq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_CLEAR);
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}
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static void combiner_unmask_irq(struct irq_data *data)
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{
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u32 mask = 1 << (data->irq % 32);
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__raw_writel(mask, combiner_base(data) + COMBINER_ENABLE_SET);
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}
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static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
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{
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struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
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struct irq_chip *chip = irq_get_chip(irq);
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unsigned int cascade_irq, combiner_irq;
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unsigned long status;
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chained_irq_enter(chip, desc);
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spin_lock(&irq_controller_lock);
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status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
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spin_unlock(&irq_controller_lock);
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status &= chip_data->irq_mask;
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if (status == 0)
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goto out;
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combiner_irq = __ffs(status);
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cascade_irq = combiner_irq + (chip_data->irq_offset & ~31);
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if (unlikely(cascade_irq >= NR_IRQS))
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do_bad_IRQ(cascade_irq, desc);
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else
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generic_handle_irq(cascade_irq);
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out:
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chained_irq_exit(chip, desc);
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}
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static struct irq_chip combiner_chip = {
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.name = "COMBINER",
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.irq_mask = combiner_mask_irq,
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.irq_unmask = combiner_unmask_irq,
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};
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void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
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{
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if (combiner_nr >= MAX_COMBINER_NR)
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BUG();
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if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
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BUG();
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irq_set_chained_handler(irq, combiner_handle_cascade_irq);
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}
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void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
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unsigned int irq_start)
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{
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unsigned int i;
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if (combiner_nr >= MAX_COMBINER_NR)
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BUG();
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combiner_data[combiner_nr].base = base;
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combiner_data[combiner_nr].irq_offset = irq_start;
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combiner_data[combiner_nr].irq_mask = 0xff << ((combiner_nr % 4) << 3);
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/* Disable all interrupts */
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__raw_writel(combiner_data[combiner_nr].irq_mask,
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base + COMBINER_ENABLE_CLEAR);
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/* Setup the Linux IRQ subsystem */
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for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
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+ MAX_IRQ_IN_COMBINER; i++) {
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irq_set_chip_and_handler(i, &combiner_chip, handle_level_irq);
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irq_set_chip_data(i, &combiner_data[combiner_nr]);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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