c7f486567c
PCIe native PME detection mechanism is based on interrupts generated by root ports or event collectors every time a PCIe device sends a PME message upstream. Once a PME message has been sent by an endpoint device and received by its root port (or event collector in the case of root complex integrated endpoints), the Requester ID from the message header is registered in the root port's Root Status register. At the same time, the PME Status bit of the Root Status register is set to indicate that there's a PME to handle. If PCIe PME interrupt is enabled for the root port, it generates an interrupt once the PME Status has been set. After receiving the interrupt, the kernel can identify the PCIe device that generated the PME using the Requester ID from the root port's Root Status register. [For details, see PCI Express Base Specification, Rev. 2.0.] Implement a driver for the PCIe PME root port service working in accordance with the above description. Based on a patch from Shaohua Li <shaohua.li@intel.com>. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
53 lines
1.3 KiB
Plaintext
53 lines
1.3 KiB
Plaintext
#
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# PCI Express Port Bus Configuration
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#
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config PCIEPORTBUS
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bool "PCI Express support"
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depends on PCI
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help
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This automatically enables PCI Express Port Bus support. Users can
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choose Native Hot-Plug support, Advanced Error Reporting support,
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Power Management Event support and Virtual Channel support to run
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on PCI Express Ports (Root or Switch).
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#
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# Include service Kconfig here
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#
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config HOTPLUG_PCI_PCIE
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tristate "PCI Express Hotplug driver"
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depends on HOTPLUG_PCI && PCIEPORTBUS
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help
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Say Y here if you have a motherboard that supports PCI Express Native
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Hotplug
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To compile this driver as a module, choose M here: the
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module will be called pciehp.
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When in doubt, say N.
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source "drivers/pci/pcie/aer/Kconfig"
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#
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# PCI Express ASPM
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#
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config PCIEASPM
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bool "PCI Express ASPM support(Experimental)"
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depends on PCI && EXPERIMENTAL && PCIEPORTBUS
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default n
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help
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This enables PCI Express ASPM (Active State Power Management) and
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Clock Power Management. ASPM supports state L0/L0s/L1.
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When in doubt, say N.
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config PCIEASPM_DEBUG
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bool "Debug PCI Express ASPM"
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depends on PCIEASPM
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default n
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help
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This enables PCI Express ASPM debug support. It will add per-device
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interface to control ASPM.
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config PCIE_PME
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def_bool y
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depends on PCIEPORTBUS && PM_RUNTIME && EXPERIMENTAL && ACPI
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