954fbc8985
We provide regs->tstate, regs->tpc, regs->tnpc and regs->u_regs[UREG_FP]. regs->tstate is necessary for: user_mode() (via perf_exclude_event()) perf_misc_flags() (via perf_prepare_sample()) regs->tpc is necessary for: perf_instruction_pointer() (via perf_prepare_sample()) and regs->u_regs[UREG_FP] is necessary for: perf_callchain() (via perf_prepare_sample()) The regs->tnpc value is provided just to be tidy. Signed-off-by: David S. Miller <davem@davemloft.net>
139 lines
3.2 KiB
ArmAsm
139 lines
3.2 KiB
ArmAsm
.align 32
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.globl __flushw_user
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.type __flushw_user,#function
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__flushw_user:
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rdpr %otherwin, %g1
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brz,pn %g1, 2f
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clr %g2
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1: save %sp, -128, %sp
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rdpr %otherwin, %g1
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brnz,pt %g1, 1b
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add %g2, 1, %g2
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1: sub %g2, 1, %g2
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brnz,pt %g2, 1b
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restore %g0, %g0, %g0
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2: retl
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nop
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.size __flushw_user,.-__flushw_user
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/* Flush %fp and %i7 to the stack for all register
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* windows active inside of the cpu. This allows
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* show_stack_trace() to avoid using an expensive
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* 'flushw'.
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*/
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.globl stack_trace_flush
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.type stack_trace_flush,#function
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stack_trace_flush:
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rdpr %pstate, %o0
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wrpr %o0, PSTATE_IE, %pstate
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rdpr %cwp, %g1
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rdpr %canrestore, %g2
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sub %g1, 1, %g3
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1: brz,pn %g2, 2f
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sub %g2, 1, %g2
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wrpr %g3, %cwp
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stx %fp, [%sp + STACK_BIAS + RW_V9_I6]
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stx %i7, [%sp + STACK_BIAS + RW_V9_I7]
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ba,pt %xcc, 1b
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sub %g3, 1, %g3
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2: wrpr %g1, %cwp
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wrpr %o0, %pstate
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retl
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nop
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.size stack_trace_flush,.-stack_trace_flush
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#ifdef CONFIG_PERF_EVENTS
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.globl perf_arch_fetch_caller_regs
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.type perf_arch_fetch_caller_regs,#function
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perf_arch_fetch_caller_regs:
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/* We always read the %pstate into %o5 since we will use
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* that to construct a fake %tstate to store into the regs.
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*/
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rdpr %pstate, %o5
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brz,pn %o2, 50f
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mov %o2, %g7
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/* Turn off interrupts while we walk around the register
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* window by hand.
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*/
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wrpr %o5, PSTATE_IE, %pstate
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/* The %canrestore tells us how many register windows are
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* still live in the chip above us, past that we have to
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* walk the frame as saved on the stack. We stash away
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* the %cwp in %g1 so we can return back to the original
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* register window.
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*/
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rdpr %cwp, %g1
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rdpr %canrestore, %g2
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sub %g1, 1, %g3
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/* We have the skip count in %g7, if it hits zero then
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* %fp/%i7 are the registers we need. Otherwise if our
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* %canrestore count maintained in %g2 hits zero we have
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* to start traversing the stack.
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*/
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10: brz,pn %g2, 4f
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sub %g2, 1, %g2
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wrpr %g3, %cwp
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subcc %g7, 1, %g7
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bne,pt %xcc, 10b
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sub %g3, 1, %g3
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/* We found the values we need in the cpu's register
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* windows.
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*/
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mov %fp, %g3
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ba,pt %xcc, 3f
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mov %i7, %g2
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50: mov %fp, %g3
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ba,pt %xcc, 2f
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mov %i7, %g2
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/* We hit the end of the valid register windows in the
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* cpu, start traversing the stack frame.
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*/
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4: mov %fp, %g3
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20: ldx [%g3 + STACK_BIAS + RW_V9_I7], %g2
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subcc %g7, 1, %g7
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bne,pn %xcc, 20b
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ldx [%g3 + STACK_BIAS + RW_V9_I6], %g3
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/* Restore the current register window position and
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* re-enable interrupts.
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*/
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3: wrpr %g1, %cwp
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wrpr %o5, %pstate
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2: stx %g3, [%o0 + PT_V9_FP]
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sllx %o5, 8, %o5
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stx %o5, [%o0 + PT_V9_TSTATE]
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stx %g2, [%o0 + PT_V9_TPC]
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add %g2, 4, %g2
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retl
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stx %g2, [%o0 + PT_V9_TNPC]
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.size perf_arch_fetch_caller_regs,.-perf_arch_fetch_caller_regs
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#endif /* CONFIG_PERF_EVENTS */
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#ifdef CONFIG_SMP
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.globl hard_smp_processor_id
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.type hard_smp_processor_id,#function
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hard_smp_processor_id:
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#endif
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.globl real_hard_smp_processor_id
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.type real_hard_smp_processor_id,#function
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real_hard_smp_processor_id:
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__GET_CPUID(%o0)
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retl
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nop
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#ifdef CONFIG_SMP
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.size hard_smp_processor_id,.-hard_smp_processor_id
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#endif
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.size real_hard_smp_processor_id,.-real_hard_smp_processor_id
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