1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
118 lines
4.9 KiB
C
118 lines
4.9 KiB
C
/*********************************************************
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* *
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* Definition of D-Link DE-620 Ethernet Pocket adapter *
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* *
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*********************************************************/
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/* DE-620's CMD port Command */
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#define CS0 0x08 /* 1->0 command strobe */
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#define ICEN 0x04 /* 0=enable DL3520 host interface */
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#define DS0 0x02 /* 1->0 data strobe 0 */
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#define DS1 0x01 /* 1->0 data strobe 1 */
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#define WDIR 0x20 /* general 0=read 1=write */
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#define RDIR 0x00 /* (not 100% confirm ) */
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#define PS2WDIR 0x00 /* ps/2 mode 1=read, 0=write */
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#define PS2RDIR 0x20
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#define IRQEN 0x10 /* 1 = enable printer IRQ line */
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#define SELECTIN 0x08 /* 1 = select printer */
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#define INITP 0x04 /* 0 = initial printer */
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#define AUTOFEED 0x02 /* 1 = printer auto form feed */
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#define STROBE 0x01 /* 0->1 data strobe */
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#define RESET 0x08
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#define NIS0 0x20 /* 0 = BNC, 1 = UTP */
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#define NCTL0 0x10
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/* DE-620 DIC Command */
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#define W_DUMMY 0x00 /* DIC reserved command */
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#define W_CR 0x20 /* DIC write command register */
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#define W_NPR 0x40 /* DIC write Next Page Register */
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#define W_TBR 0x60 /* DIC write Tx Byte Count 1 reg */
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#define W_RSA 0x80 /* DIC write Remote Start Addr 1 */
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/* DE-620's STAT port bits 7-4 */
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#define EMPTY 0x80 /* 1 = receive buffer empty */
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#define INTLEVEL 0x40 /* 1 = interrupt level is high */
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#define TXBF1 0x20 /* 1 = transmit buffer 1 is in use */
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#define TXBF0 0x10 /* 1 = transmit buffer 0 is in use */
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#define READY 0x08 /* 1 = h/w ready to accept cmd/data */
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/* IDC 1 Command */
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#define W_RSA1 0xa0 /* write remote start address 1 */
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#define W_RSA0 0xa1 /* write remote start address 0 */
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#define W_NPRF 0xa2 /* write next page register NPR15-NPR8 */
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#define W_DFR 0xa3 /* write delay factor register */
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#define W_CPR 0xa4 /* write current page register */
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#define W_SPR 0xa5 /* write start page register */
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#define W_EPR 0xa6 /* write end page register */
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#define W_SCR 0xa7 /* write system configuration register */
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#define W_TCR 0xa8 /* write Transceiver Configuration reg */
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#define W_EIP 0xa9 /* write EEPM Interface port */
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#define W_PAR0 0xaa /* write physical address register 0 */
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#define W_PAR1 0xab /* write physical address register 1 */
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#define W_PAR2 0xac /* write physical address register 2 */
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#define W_PAR3 0xad /* write physical address register 3 */
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#define W_PAR4 0xae /* write physical address register 4 */
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#define W_PAR5 0xaf /* write physical address register 5 */
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/* IDC 2 Command */
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#define R_STS 0xc0 /* read status register */
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#define R_CPR 0xc1 /* read current page register */
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#define R_BPR 0xc2 /* read boundary page register */
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#define R_TDR 0xc3 /* read time domain reflectometry reg */
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/* STATUS Register */
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#define EEDI 0x80 /* EEPM DO pin */
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#define TXSUC 0x40 /* tx success */
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#define T16 0x20 /* tx fail 16 times */
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#define TS1 0x40 /* 0=Tx success, 1=T16 */
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#define TS0 0x20 /* 0=Tx success, 1=T16 */
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#define RXGOOD 0x10 /* rx a good packet */
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#define RXCRC 0x08 /* rx a CRC error packet */
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#define RXSHORT 0x04 /* rx a short packet */
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#define COLS 0x02 /* coaxial collision status */
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#define LNKS 0x01 /* UTP link status */
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/* Command Register */
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#define CLEAR 0x10 /* reset part of hardware */
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#define NOPER 0x08 /* No Operation */
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#define RNOP 0x08
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#define RRA 0x06 /* After RR then auto-advance NPR & BPR(=NPR-1) */
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#define RRN 0x04 /* Normal Remote Read mode */
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#define RW1 0x02 /* Remote Write tx buffer 1 ( page 6 - 11 ) */
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#define RW0 0x00 /* Remote Write tx buffer 0 ( page 0 - 5 ) */
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#define TXEN 0x01 /* 0->1 tx enable */
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/* System Configuration Register */
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#define TESTON 0x80 /* test host data transfer reliability */
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#define SLEEP 0x40 /* sleep mode */
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#if 0
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#define FASTMODE 0x04 /* fast mode for intel 82360SL fast mode */
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#define BYTEMODE 0x02 /* byte mode */
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#else
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#define FASTMODE 0x20 /* fast mode for intel 82360SL fast mode */
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#define BYTEMODE 0x10 /* byte mode */
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#endif
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#define NIBBLEMODE 0x00 /* nibble mode */
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#define IRQINV 0x08 /* turn off IRQ line inverter */
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#define IRQNML 0x00 /* turn on IRQ line inverter */
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#define INTON 0x04
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#define AUTOFFSET 0x02 /* auto shift address to TPR+12 */
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#define AUTOTX 0x01 /* auto tx when leave RW mode */
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/* Transceiver Configuration Register */
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#define JABBER 0x80 /* generate jabber condition */
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#define TXSUCINT 0x40 /* enable tx success interrupt */
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#define T16INT 0x20 /* enable T16 interrupt */
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#define RXERRPKT 0x10 /* accept CRC error or short packet */
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#define EXTERNALB2 0x0C /* external loopback 2 */
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#define EXTERNALB1 0x08 /* external loopback 1 */
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#define INTERNALB 0x04 /* internal loopback */
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#define NMLOPERATE 0x00 /* normal operation */
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#define RXPBM 0x03 /* rx physical, broadcast, multicast */
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#define RXPB 0x02 /* rx physical, broadcast */
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#define RXALL 0x01 /* rx all packet */
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#define RXOFF 0x00 /* rx disable */
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