13eb4ab8ca
Signed-off-by: Raymond Yau <superquad.vortex2@gmail.com> Signed-off-by: Takashi Iwai <tiwai@suse.de>
225 lines
6.8 KiB
C
225 lines
6.8 KiB
C
/*
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Aureal Advantage Soundcard driver.
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*/
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#define CHIP_AU8810
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#define CARD_NAME "Aureal Advantage"
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#define CARD_NAME_SHORT "au8810"
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#define NR_ADB 0x10
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#define NR_WT 0x00
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#define NR_SRC 0x10
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#define NR_A3D 0x10
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#define NR_MIXIN 0x20
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#define NR_MIXOUT 0x10
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/* ADBDMA */
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#define VORTEX_ADBDMA_STAT 0x27e00 /* read only, subbuffer, DMA pos */
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#define POS_MASK 0x00000fff
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#define POS_SHIFT 0x0
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#define ADB_SUBBUF_MASK 0x00003000 /* ADB only. */
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#define ADB_SUBBUF_SHIFT 0xc /* ADB only. */
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#define VORTEX_ADBDMA_CTRL 0x27180 /* write only; format, flags, DMA pos */
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#define OFFSET_MASK 0x00000fff
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#define OFFSET_SHIFT 0x0
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#define IE_MASK 0x00001000 /* interrupt enable. */
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#define IE_SHIFT 0xc
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#define DIR_MASK 0x00002000 /* Direction */
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#define DIR_SHIFT 0xd
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#define FMT_MASK 0x0003c000
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#define FMT_SHIFT 0xe
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// The ADB masks and shift also are valid for the wtdma, except if specified otherwise.
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#define VORTEX_ADBDMA_BUFCFG0 0x27100
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#define VORTEX_ADBDMA_BUFCFG1 0x27104
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#define VORTEX_ADBDMA_BUFBASE 0x27000
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#define VORTEX_ADBDMA_START 0x27c00 /* Which subbuffer starts */
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#define VORTEX_ADBDMA_STATUS 0x27A90 /* stored at AdbDma->this_10 / 2 DWORD in size. */
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/* WTDMA */
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#define VORTEX_WTDMA_CTRL 0x27fd8 /* format, DMA pos */
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#define VORTEX_WTDMA_STAT 0x27fe8 /* DMA subbuf, DMA pos */
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#define WT_SUBBUF_MASK 0x3
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#define WT_SUBBUF_SHIFT 0xc
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#define VORTEX_WTDMA_BUFBASE 0x27fc0
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#define VORTEX_WTDMA_BUFCFG0 0x27fd0
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#define VORTEX_WTDMA_BUFCFG1 0x27fd4
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#define VORTEX_WTDMA_START 0x27fe4 /* which subbuffer is first */
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/* ADB */
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#define VORTEX_ADB_SR 0x28400 /* Samplerates enable/disable */
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#define VORTEX_ADB_RTBASE 0x28000
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#define VORTEX_ADB_RTBASE_COUNT 173
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#define VORTEX_ADB_CHNBASE 0x282b4
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#define VORTEX_ADB_CHNBASE_COUNT 24
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#define ROUTE_MASK 0xffff
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#define SOURCE_MASK 0xff00
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#define ADB_MASK 0xff
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#define ADB_SHIFT 0x8
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/* ADB address */
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#define OFFSET_ADBDMA 0x00
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#define OFFSET_SRCIN 0x40
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#define OFFSET_SRCOUT 0x20
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#define OFFSET_MIXIN 0x50
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#define OFFSET_MIXOUT 0x30
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#define OFFSET_CODECIN 0x70
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#define OFFSET_CODECOUT 0x88
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#define OFFSET_SPORTIN 0x78 /* ch 0x13 */
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#define OFFSET_SPORTOUT 0x90
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#define OFFSET_SPDIFOUT 0x92 /* ch 0x14 check this! */
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#define OFFSET_EQIN 0xa0
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#define OFFSET_EQOUT 0x7e /* 2 routes on ch 0x11 */
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#define OFFSET_XTALKOUT 0x66 /* crosstalk canceller (source) */
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#define OFFSET_XTALKIN 0x96 /* crosstalk canceller (sink) */
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#define OFFSET_A3DIN 0x70 /* ADB sink. */
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#define OFFSET_A3DOUT 0xA6 /* ADB source. 2 routes per slice = 8 */
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#define OFFSET_EFXIN 0x80 /* ADB sink. */
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#define OFFSET_EFXOUT 0x68 /* ADB source. */
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/* ADB route translate helper */
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#define ADB_DMA(x) (x)
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#define ADB_SRCOUT(x) (x + OFFSET_SRCOUT)
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#define ADB_SRCIN(x) (x + OFFSET_SRCIN)
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#define ADB_MIXOUT(x) (x + OFFSET_MIXOUT)
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#define ADB_MIXIN(x) (x + OFFSET_MIXIN)
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#define ADB_CODECIN(x) (x + OFFSET_CODECIN)
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#define ADB_CODECOUT(x) (x + OFFSET_CODECOUT)
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#define ADB_SPORTIN(x) (x + OFFSET_SPORTIN)
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#define ADB_SPORTOUT(x) (x + OFFSET_SPORTOUT)
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#define ADB_SPDIFOUT(x) (x + OFFSET_SPDIFOUT)
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#define ADB_EQIN(x) (x + OFFSET_EQIN)
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#define ADB_EQOUT(x) (x + OFFSET_EQOUT)
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#define ADB_A3DOUT(x) (x + OFFSET_A3DOUT) /* 0x10 A3D blocks */
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#define ADB_A3DIN(x) (x + OFFSET_A3DIN)
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#define ADB_XTALKIN(x) (x + OFFSET_XTALKIN)
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#define ADB_XTALKOUT(x) (x + OFFSET_XTALKOUT)
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#define MIX_OUTL 0xe
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#define MIX_OUTR 0xf
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#define MIX_INL 0x1e
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#define MIX_INR 0x1f
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#define MIX_DEFIGAIN 0x08 /* 0x8 => 6dB */
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#define MIX_DEFOGAIN 0x08
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/* MIXER */
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#define VORTEX_MIXER_SR 0x21f00
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#define VORTEX_MIXER_CLIP 0x21f80
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#define VORTEX_MIXER_CHNBASE 0x21e40
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#define VORTEX_MIXER_RTBASE 0x21e00
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#define MIXER_RTBASE_SIZE 0x38
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#define VORTEX_MIX_ENIN 0x21a00 /* Input enable bits. 4 bits wide. */
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#define VORTEX_MIX_SMP 0x21c00 /* AU8820: 0x9c00 */
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/* MIX */
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#define VORTEX_MIX_INVOL_A 0x21000 /* in? */
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#define VORTEX_MIX_INVOL_B 0x20000 /* out? */
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#define VORTEX_MIX_VOL_A 0x21800
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#define VORTEX_MIX_VOL_B 0x20800
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#define VOL_MIN 0x80 /* Input volume when muted. */
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#define VOL_MAX 0x7f /* FIXME: Not confirmed! Just guessed. */
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/* SRC */
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#define VORTEX_SRC_CHNBASE 0x26c40
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#define VORTEX_SRC_RTBASE 0x26c00
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#define VORTEX_SRCBLOCK_SR 0x26cc0
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#define VORTEX_SRC_SOURCE 0x26cc4
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#define VORTEX_SRC_SOURCESIZE 0x26cc8
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/* Params
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0x26e00 : 1 U0
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0x26e40 : 2 CR
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0x26e80 : 3 U3
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0x26ec0 : 4 DRIFT1
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0x26f00 : 5 U1
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0x26f40 : 6 DRIFT2
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0x26f80 : 7 U2 : Target rate, direction
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*/
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#define VORTEX_SRC_CONVRATIO 0x26e40
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#define VORTEX_SRC_DRIFT0 0x26e80
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#define VORTEX_SRC_DRIFT1 0x26ec0
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#define VORTEX_SRC_DRIFT2 0x26f40
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#define VORTEX_SRC_U0 0x26e00
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#define U0_SLOWLOCK 0x200
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#define VORTEX_SRC_U1 0x26f00
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#define VORTEX_SRC_U2 0x26f80
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#define VORTEX_SRC_DATA 0x26800 /* 0xc800 */
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#define VORTEX_SRC_DATA0 0x26000
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/* FIFO */
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#define VORTEX_FIFO_ADBCTRL 0x16100 /* Control bits. */
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#define VORTEX_FIFO_WTCTRL 0x16000
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#define FIFO_RDONLY 0x00000001
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#define FIFO_CTRL 0x00000002 /* Allow ctrl. ? */
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#define FIFO_VALID 0x00000010
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#define FIFO_EMPTY 0x00000020
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#define FIFO_U0 0x00001000 /* Unknown. */
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#define FIFO_U1 0x00010000
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#define FIFO_SIZE_BITS 5
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#define FIFO_SIZE (1<<FIFO_SIZE_BITS) // 0x20
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#define FIFO_MASK (FIFO_SIZE-1) //0x1f /* at shift left 0xc */
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//#define FIFO_MASK 0x1f /* at shift left 0xb */
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//#define FIFO_SIZE 0x20
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#define FIFO_BITS 0x03880000
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#define VORTEX_FIFO_ADBDATA 0x14000
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#define VORTEX_FIFO_WTDATA 0x10000
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/* CODEC */
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#define VORTEX_CODEC_CTRL 0x29184
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#define VORTEX_CODEC_EN 0x29190
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#define EN_CODEC0 0x00000300
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#define EN_AC98 0x00000c00 /* Modem AC98 slots. */
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#define EN_CODEC1 0x00003000
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#define EN_CODEC (EN_CODEC0 | EN_CODEC1)
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#define EN_SPORT 0x00030000
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#define EN_SPDIF 0x000c0000
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#define VORTEX_CODEC_CHN 0x29080
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#define VORTEX_CODEC_IO 0x29188
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/* SPDIF */
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#define VORTEX_SPDIF_FLAGS 0x2205c
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#define VORTEX_SPDIF_CFG0 0x291D0
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#define VORTEX_SPDIF_CFG1 0x291D4
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#define VORTEX_SPDIF_SMPRATE 0x29194
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/* Sample timer */
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#define VORTEX_SMP_TIME 0x29198
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#define VORTEX_MODEM_CTRL 0x291ac
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/* IRQ */
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#define VORTEX_IRQ_SOURCE 0x2a000 /* Interrupt source flags. */
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#define VORTEX_IRQ_CTRL 0x2a004 /* Interrupt source mask. */
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#define VORTEX_STAT 0x2a008 /* Status */
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#define VORTEX_CTRL 0x2a00c
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#define CTRL_MIDI_EN 0x00000001
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#define CTRL_MIDI_PORT 0x00000060
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#define CTRL_GAME_EN 0x00000008
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#define CTRL_GAME_PORT 0x00000e00
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//#define CTRL_IRQ_ENABLE 0x01004000
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#define CTRL_IRQ_ENABLE 0x00004000
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/* write: Timer period config / read: TIMER IRQ ack. */
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#define VORTEX_IRQ_STAT 0x2919c
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/* DMA */
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#define VORTEX_ENGINE_CTRL 0x27ae8
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#define ENGINE_INIT 0x1380000
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/* MIDI *//* GAME. */
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#define VORTEX_MIDI_DATA 0x28800
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#define VORTEX_MIDI_CMD 0x28804 /* Write command / Read status */
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#define VORTEX_CTRL2 0x2880c
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#define CTRL2_GAME_ADCMODE 0x40
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#define VORTEX_GAME_LEGACY 0x28808
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#define VORTEX_GAME_AXIS 0x28810
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#define AXIS_SIZE 4
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#define AXIS_RANGE 0x1fff
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