0bb3184df5
Trival patch for CPU hotplug. In CPU identify part, only did cleaup for intel CPUs. Need do for other CPUs if they support S3 SMP. Signed-off-by: Li Shaohua<shaohua.li@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
599 lines
16 KiB
C
599 lines
16 KiB
C
/*
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* Routines to indentify caches on Intel CPU.
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*
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* Changes:
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* Venkatesh Pallipadi : Adding cache identification through cpuid(4)
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*/
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/device.h>
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#include <linux/compiler.h>
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#include <linux/cpu.h>
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#include <asm/processor.h>
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#include <asm/smp.h>
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#define LVL_1_INST 1
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#define LVL_1_DATA 2
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#define LVL_2 3
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#define LVL_3 4
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#define LVL_TRACE 5
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struct _cache_table
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{
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unsigned char descriptor;
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char cache_type;
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short size;
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};
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/* all the cache descriptor types we care about (no TLB or trace cache entries) */
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static struct _cache_table cache_table[] __devinitdata =
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{
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{ 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
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{ 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
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{ 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
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{ 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
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{ 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x23, LVL_3, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x25, LVL_3, 2048 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x29, LVL_3, 4096 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x2c, LVL_1_DATA, 32 }, /* 8-way set assoc, 64 byte line size */
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{ 0x30, LVL_1_INST, 32 }, /* 8-way set assoc, 64 byte line size */
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{ 0x39, LVL_2, 128 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x3b, LVL_2, 128 }, /* 2-way set assoc, sectored cache, 64 byte line size */
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{ 0x3c, LVL_2, 256 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x41, LVL_2, 128 }, /* 4-way set assoc, 32 byte line size */
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{ 0x42, LVL_2, 256 }, /* 4-way set assoc, 32 byte line size */
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{ 0x43, LVL_2, 512 }, /* 4-way set assoc, 32 byte line size */
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{ 0x44, LVL_2, 1024 }, /* 4-way set assoc, 32 byte line size */
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{ 0x45, LVL_2, 2048 }, /* 4-way set assoc, 32 byte line size */
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{ 0x60, LVL_1_DATA, 16 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x66, LVL_1_DATA, 8 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x67, LVL_1_DATA, 16 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x68, LVL_1_DATA, 32 }, /* 4-way set assoc, sectored cache, 64 byte line size */
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{ 0x70, LVL_TRACE, 12 }, /* 8-way set assoc */
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{ 0x71, LVL_TRACE, 16 }, /* 8-way set assoc */
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{ 0x72, LVL_TRACE, 32 }, /* 8-way set assoc */
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{ 0x78, LVL_2, 1024 }, /* 4-way set assoc, 64 byte line size */
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{ 0x79, LVL_2, 128 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7a, LVL_2, 256 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7b, LVL_2, 512 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7c, LVL_2, 1024 }, /* 8-way set assoc, sectored cache, 64 byte line size */
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{ 0x7d, LVL_2, 2048 }, /* 8-way set assoc, 64 byte line size */
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{ 0x7f, LVL_2, 512 }, /* 2-way set assoc, 64 byte line size */
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{ 0x82, LVL_2, 256 }, /* 8-way set assoc, 32 byte line size */
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{ 0x83, LVL_2, 512 }, /* 8-way set assoc, 32 byte line size */
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{ 0x84, LVL_2, 1024 }, /* 8-way set assoc, 32 byte line size */
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{ 0x85, LVL_2, 2048 }, /* 8-way set assoc, 32 byte line size */
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{ 0x86, LVL_2, 512 }, /* 4-way set assoc, 64 byte line size */
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{ 0x87, LVL_2, 1024 }, /* 8-way set assoc, 64 byte line size */
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{ 0x00, 0, 0}
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};
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enum _cache_type
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{
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CACHE_TYPE_NULL = 0,
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CACHE_TYPE_DATA = 1,
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CACHE_TYPE_INST = 2,
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CACHE_TYPE_UNIFIED = 3
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};
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union _cpuid4_leaf_eax {
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struct {
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enum _cache_type type:5;
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unsigned int level:3;
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unsigned int is_self_initializing:1;
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unsigned int is_fully_associative:1;
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unsigned int reserved:4;
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unsigned int num_threads_sharing:12;
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unsigned int num_cores_on_die:6;
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} split;
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u32 full;
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};
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union _cpuid4_leaf_ebx {
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struct {
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unsigned int coherency_line_size:12;
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unsigned int physical_line_partition:10;
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unsigned int ways_of_associativity:10;
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} split;
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u32 full;
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};
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union _cpuid4_leaf_ecx {
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struct {
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unsigned int number_of_sets:32;
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} split;
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u32 full;
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};
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struct _cpuid4_info {
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union _cpuid4_leaf_eax eax;
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union _cpuid4_leaf_ebx ebx;
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union _cpuid4_leaf_ecx ecx;
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unsigned long size;
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cpumask_t shared_cpu_map;
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};
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#define MAX_CACHE_LEAVES 4
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static unsigned short num_cache_leaves;
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static int __devinit cpuid4_cache_lookup(int index, struct _cpuid4_info *this_leaf)
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{
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unsigned int eax, ebx, ecx, edx;
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union _cpuid4_leaf_eax cache_eax;
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cpuid_count(4, index, &eax, &ebx, &ecx, &edx);
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cache_eax.full = eax;
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if (cache_eax.split.type == CACHE_TYPE_NULL)
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return -1;
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this_leaf->eax.full = eax;
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this_leaf->ebx.full = ebx;
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this_leaf->ecx.full = ecx;
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this_leaf->size = (this_leaf->ecx.split.number_of_sets + 1) *
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(this_leaf->ebx.split.coherency_line_size + 1) *
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(this_leaf->ebx.split.physical_line_partition + 1) *
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(this_leaf->ebx.split.ways_of_associativity + 1);
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return 0;
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}
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static int __init find_num_cache_leaves(void)
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{
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unsigned int eax, ebx, ecx, edx;
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union _cpuid4_leaf_eax cache_eax;
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int i;
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int retval;
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retval = MAX_CACHE_LEAVES;
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/* Do cpuid(4) loop to find out num_cache_leaves */
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for (i = 0; i < MAX_CACHE_LEAVES; i++) {
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cpuid_count(4, i, &eax, &ebx, &ecx, &edx);
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cache_eax.full = eax;
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if (cache_eax.split.type == CACHE_TYPE_NULL) {
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retval = i;
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break;
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}
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}
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return retval;
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}
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unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
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{
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unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
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unsigned int new_l1d = 0, new_l1i = 0; /* Cache sizes from cpuid(4) */
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unsigned int new_l2 = 0, new_l3 = 0, i; /* Cache sizes from cpuid(4) */
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if (c->cpuid_level > 4) {
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static int is_initialized;
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if (is_initialized == 0) {
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/* Init num_cache_leaves from boot CPU */
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num_cache_leaves = find_num_cache_leaves();
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is_initialized++;
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}
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/*
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* Whenever possible use cpuid(4), deterministic cache
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* parameters cpuid leaf to find the cache details
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*/
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for (i = 0; i < num_cache_leaves; i++) {
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struct _cpuid4_info this_leaf;
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int retval;
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retval = cpuid4_cache_lookup(i, &this_leaf);
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if (retval >= 0) {
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switch(this_leaf.eax.split.level) {
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case 1:
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if (this_leaf.eax.split.type ==
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CACHE_TYPE_DATA)
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new_l1d = this_leaf.size/1024;
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else if (this_leaf.eax.split.type ==
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CACHE_TYPE_INST)
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new_l1i = this_leaf.size/1024;
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break;
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case 2:
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new_l2 = this_leaf.size/1024;
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break;
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case 3:
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new_l3 = this_leaf.size/1024;
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break;
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default:
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break;
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}
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}
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}
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}
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if (c->cpuid_level > 1) {
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/* supports eax=2 call */
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int i, j, n;
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int regs[4];
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unsigned char *dp = (unsigned char *)regs;
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/* Number of times to iterate */
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n = cpuid_eax(2) & 0xFF;
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for ( i = 0 ; i < n ; i++ ) {
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cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
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/* If bit 31 is set, this is an unknown format */
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for ( j = 0 ; j < 3 ; j++ ) {
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if ( regs[j] < 0 ) regs[j] = 0;
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}
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/* Byte 0 is level count, not a descriptor */
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for ( j = 1 ; j < 16 ; j++ ) {
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unsigned char des = dp[j];
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unsigned char k = 0;
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/* look up this descriptor in the table */
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while (cache_table[k].descriptor != 0)
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{
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if (cache_table[k].descriptor == des) {
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switch (cache_table[k].cache_type) {
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case LVL_1_INST:
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l1i += cache_table[k].size;
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break;
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case LVL_1_DATA:
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l1d += cache_table[k].size;
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break;
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case LVL_2:
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l2 += cache_table[k].size;
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break;
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case LVL_3:
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l3 += cache_table[k].size;
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break;
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case LVL_TRACE:
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trace += cache_table[k].size;
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break;
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}
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break;
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}
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k++;
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}
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}
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}
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if (new_l1d)
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l1d = new_l1d;
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if (new_l1i)
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l1i = new_l1i;
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if (new_l2)
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l2 = new_l2;
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if (new_l3)
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l3 = new_l3;
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if ( trace )
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printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
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else if ( l1i )
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printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
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if ( l1d )
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printk(", L1 D cache: %dK\n", l1d);
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else
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printk("\n");
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if ( l2 )
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printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
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if ( l3 )
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printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
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/*
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* This assumes the L3 cache is shared; it typically lives in
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* the northbridge. The L1 caches are included by the L2
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* cache, and so should not be included for the purpose of
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* SMP switching weights.
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*/
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c->x86_cache_size = l2 ? l2 : (l1i+l1d);
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}
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return l2;
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}
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/* pointer to _cpuid4_info array (for each cache leaf) */
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static struct _cpuid4_info *cpuid4_info[NR_CPUS];
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#define CPUID4_INFO_IDX(x,y) (&((cpuid4_info[x])[y]))
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#ifdef CONFIG_SMP
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static void __devinit cache_shared_cpu_map_setup(unsigned int cpu, int index)
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{
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struct _cpuid4_info *this_leaf;
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unsigned long num_threads_sharing;
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this_leaf = CPUID4_INFO_IDX(cpu, index);
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num_threads_sharing = 1 + this_leaf->eax.split.num_threads_sharing;
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if (num_threads_sharing == 1)
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cpu_set(cpu, this_leaf->shared_cpu_map);
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#ifdef CONFIG_X86_HT
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else if (num_threads_sharing == smp_num_siblings)
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this_leaf->shared_cpu_map = cpu_sibling_map[cpu];
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#endif
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else
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printk(KERN_INFO "Number of CPUs sharing cache didn't match "
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"any known set of CPUs\n");
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}
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#else
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static void __init cache_shared_cpu_map_setup(unsigned int cpu, int index) {}
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#endif
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static void free_cache_attributes(unsigned int cpu)
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{
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kfree(cpuid4_info[cpu]);
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cpuid4_info[cpu] = NULL;
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}
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static int __devinit detect_cache_attributes(unsigned int cpu)
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{
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struct _cpuid4_info *this_leaf;
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unsigned long j;
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int retval;
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if (num_cache_leaves == 0)
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return -ENOENT;
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cpuid4_info[cpu] = kmalloc(
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sizeof(struct _cpuid4_info) * num_cache_leaves, GFP_KERNEL);
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if (unlikely(cpuid4_info[cpu] == NULL))
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return -ENOMEM;
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memset(cpuid4_info[cpu], 0,
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sizeof(struct _cpuid4_info) * num_cache_leaves);
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/* Do cpuid and store the results */
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for (j = 0; j < num_cache_leaves; j++) {
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this_leaf = CPUID4_INFO_IDX(cpu, j);
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retval = cpuid4_cache_lookup(j, this_leaf);
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if (unlikely(retval < 0))
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goto err_out;
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cache_shared_cpu_map_setup(cpu, j);
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}
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return 0;
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err_out:
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free_cache_attributes(cpu);
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return -ENOMEM;
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}
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#ifdef CONFIG_SYSFS
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#include <linux/kobject.h>
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#include <linux/sysfs.h>
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extern struct sysdev_class cpu_sysdev_class; /* from drivers/base/cpu.c */
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/* pointer to kobject for cpuX/cache */
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static struct kobject * cache_kobject[NR_CPUS];
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struct _index_kobject {
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struct kobject kobj;
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unsigned int cpu;
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unsigned short index;
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};
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/* pointer to array of kobjects for cpuX/cache/indexY */
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static struct _index_kobject *index_kobject[NR_CPUS];
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#define INDEX_KOBJECT_PTR(x,y) (&((index_kobject[x])[y]))
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#define show_one_plus(file_name, object, val) \
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static ssize_t show_##file_name \
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(struct _cpuid4_info *this_leaf, char *buf) \
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{ \
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return sprintf (buf, "%lu\n", (unsigned long)this_leaf->object + val); \
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}
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show_one_plus(level, eax.split.level, 0);
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show_one_plus(coherency_line_size, ebx.split.coherency_line_size, 1);
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show_one_plus(physical_line_partition, ebx.split.physical_line_partition, 1);
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show_one_plus(ways_of_associativity, ebx.split.ways_of_associativity, 1);
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show_one_plus(number_of_sets, ecx.split.number_of_sets, 1);
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static ssize_t show_size(struct _cpuid4_info *this_leaf, char *buf)
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{
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return sprintf (buf, "%luK\n", this_leaf->size / 1024);
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}
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static ssize_t show_shared_cpu_map(struct _cpuid4_info *this_leaf, char *buf)
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{
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char mask_str[NR_CPUS];
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cpumask_scnprintf(mask_str, NR_CPUS, this_leaf->shared_cpu_map);
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return sprintf(buf, "%s\n", mask_str);
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}
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static ssize_t show_type(struct _cpuid4_info *this_leaf, char *buf) {
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switch(this_leaf->eax.split.type) {
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case CACHE_TYPE_DATA:
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return sprintf(buf, "Data\n");
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break;
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case CACHE_TYPE_INST:
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return sprintf(buf, "Instruction\n");
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break;
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case CACHE_TYPE_UNIFIED:
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return sprintf(buf, "Unified\n");
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break;
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default:
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return sprintf(buf, "Unknown\n");
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break;
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}
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}
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struct _cache_attr {
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struct attribute attr;
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ssize_t (*show)(struct _cpuid4_info *, char *);
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ssize_t (*store)(struct _cpuid4_info *, const char *, size_t count);
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};
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#define define_one_ro(_name) \
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static struct _cache_attr _name = \
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__ATTR(_name, 0444, show_##_name, NULL)
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define_one_ro(level);
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define_one_ro(type);
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define_one_ro(coherency_line_size);
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define_one_ro(physical_line_partition);
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define_one_ro(ways_of_associativity);
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define_one_ro(number_of_sets);
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define_one_ro(size);
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define_one_ro(shared_cpu_map);
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static struct attribute * default_attrs[] = {
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&type.attr,
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&level.attr,
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&coherency_line_size.attr,
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&physical_line_partition.attr,
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&ways_of_associativity.attr,
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&number_of_sets.attr,
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&size.attr,
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&shared_cpu_map.attr,
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NULL
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};
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#define to_object(k) container_of(k, struct _index_kobject, kobj)
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#define to_attr(a) container_of(a, struct _cache_attr, attr)
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static ssize_t show(struct kobject * kobj, struct attribute * attr, char * buf)
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{
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struct _cache_attr *fattr = to_attr(attr);
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struct _index_kobject *this_leaf = to_object(kobj);
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ssize_t ret;
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ret = fattr->show ?
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fattr->show(CPUID4_INFO_IDX(this_leaf->cpu, this_leaf->index),
|
|
buf) :
|
|
0;
|
|
return ret;
|
|
}
|
|
|
|
static ssize_t store(struct kobject * kobj, struct attribute * attr,
|
|
const char * buf, size_t count)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static struct sysfs_ops sysfs_ops = {
|
|
.show = show,
|
|
.store = store,
|
|
};
|
|
|
|
static struct kobj_type ktype_cache = {
|
|
.sysfs_ops = &sysfs_ops,
|
|
.default_attrs = default_attrs,
|
|
};
|
|
|
|
static struct kobj_type ktype_percpu_entry = {
|
|
.sysfs_ops = &sysfs_ops,
|
|
};
|
|
|
|
static void cpuid4_cache_sysfs_exit(unsigned int cpu)
|
|
{
|
|
kfree(cache_kobject[cpu]);
|
|
kfree(index_kobject[cpu]);
|
|
cache_kobject[cpu] = NULL;
|
|
index_kobject[cpu] = NULL;
|
|
free_cache_attributes(cpu);
|
|
}
|
|
|
|
static int __devinit cpuid4_cache_sysfs_init(unsigned int cpu)
|
|
{
|
|
|
|
if (num_cache_leaves == 0)
|
|
return -ENOENT;
|
|
|
|
detect_cache_attributes(cpu);
|
|
if (cpuid4_info[cpu] == NULL)
|
|
return -ENOENT;
|
|
|
|
/* Allocate all required memory */
|
|
cache_kobject[cpu] = kmalloc(sizeof(struct kobject), GFP_KERNEL);
|
|
if (unlikely(cache_kobject[cpu] == NULL))
|
|
goto err_out;
|
|
memset(cache_kobject[cpu], 0, sizeof(struct kobject));
|
|
|
|
index_kobject[cpu] = kmalloc(
|
|
sizeof(struct _index_kobject ) * num_cache_leaves, GFP_KERNEL);
|
|
if (unlikely(index_kobject[cpu] == NULL))
|
|
goto err_out;
|
|
memset(index_kobject[cpu], 0,
|
|
sizeof(struct _index_kobject) * num_cache_leaves);
|
|
|
|
return 0;
|
|
|
|
err_out:
|
|
cpuid4_cache_sysfs_exit(cpu);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Add/Remove cache interface for CPU device */
|
|
static int __devinit cache_add_dev(struct sys_device * sys_dev)
|
|
{
|
|
unsigned int cpu = sys_dev->id;
|
|
unsigned long i, j;
|
|
struct _index_kobject *this_object;
|
|
int retval = 0;
|
|
|
|
retval = cpuid4_cache_sysfs_init(cpu);
|
|
if (unlikely(retval < 0))
|
|
return retval;
|
|
|
|
cache_kobject[cpu]->parent = &sys_dev->kobj;
|
|
kobject_set_name(cache_kobject[cpu], "%s", "cache");
|
|
cache_kobject[cpu]->ktype = &ktype_percpu_entry;
|
|
retval = kobject_register(cache_kobject[cpu]);
|
|
|
|
for (i = 0; i < num_cache_leaves; i++) {
|
|
this_object = INDEX_KOBJECT_PTR(cpu,i);
|
|
this_object->cpu = cpu;
|
|
this_object->index = i;
|
|
this_object->kobj.parent = cache_kobject[cpu];
|
|
kobject_set_name(&(this_object->kobj), "index%1lu", i);
|
|
this_object->kobj.ktype = &ktype_cache;
|
|
retval = kobject_register(&(this_object->kobj));
|
|
if (unlikely(retval)) {
|
|
for (j = 0; j < i; j++) {
|
|
kobject_unregister(
|
|
&(INDEX_KOBJECT_PTR(cpu,j)->kobj));
|
|
}
|
|
kobject_unregister(cache_kobject[cpu]);
|
|
cpuid4_cache_sysfs_exit(cpu);
|
|
break;
|
|
}
|
|
}
|
|
return retval;
|
|
}
|
|
|
|
static int __devexit cache_remove_dev(struct sys_device * sys_dev)
|
|
{
|
|
unsigned int cpu = sys_dev->id;
|
|
unsigned long i;
|
|
|
|
for (i = 0; i < num_cache_leaves; i++)
|
|
kobject_unregister(&(INDEX_KOBJECT_PTR(cpu,i)->kobj));
|
|
kobject_unregister(cache_kobject[cpu]);
|
|
cpuid4_cache_sysfs_exit(cpu);
|
|
return 0;
|
|
}
|
|
|
|
static struct sysdev_driver cache_sysdev_driver = {
|
|
.add = cache_add_dev,
|
|
.remove = __devexit_p(cache_remove_dev),
|
|
};
|
|
|
|
/* Register/Unregister the cpu_cache driver */
|
|
static int __devinit cache_register_driver(void)
|
|
{
|
|
if (num_cache_leaves == 0)
|
|
return 0;
|
|
|
|
return sysdev_driver_register(&cpu_sysdev_class,&cache_sysdev_driver);
|
|
}
|
|
|
|
device_initcall(cache_register_driver);
|
|
|
|
#endif
|
|
|