1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
837 lines
22 KiB
C
837 lines
22 KiB
C
/*
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*
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* BRIEF MODULE DESCRIPTION
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* The Descriptor Based DMA channel manager that first appeared
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* on the Au1550. I started with dma.c, but I think all that is
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* left is this initial comment :-)
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*
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* Copyright 2004 Embedded Edge, LLC
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* dan@embeddededge.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <asm/mach-au1x00/au1000.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/system.h>
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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/*
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* The Descriptor Based DMA supports up to 16 channels.
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*
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* There are 32 devices defined. We keep an internal structure
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* of devices using these channels, along with additional
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* information.
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*
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* We allocate the descriptors and allow access to them through various
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* functions. The drivers allocate the data buffers and assign them
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* to the descriptors.
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*/
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static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
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/* I couldn't find a macro that did this......
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*/
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#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
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static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
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static int dbdma_initialized;
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static void au1xxx_dbdma_init(void);
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typedef struct dbdma_device_table {
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u32 dev_id;
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u32 dev_flags;
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u32 dev_tsize;
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u32 dev_devwidth;
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u32 dev_physaddr; /* If FIFO */
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u32 dev_intlevel;
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u32 dev_intpolarity;
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} dbdev_tab_t;
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typedef struct dbdma_chan_config {
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u32 chan_flags;
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u32 chan_index;
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dbdev_tab_t *chan_src;
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dbdev_tab_t *chan_dest;
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au1x_dma_chan_t *chan_ptr;
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au1x_ddma_desc_t *chan_desc_base;
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au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
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void *chan_callparam;
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void (*chan_callback)(int, void *, struct pt_regs *);
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} chan_tab_t;
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#define DEV_FLAGS_INUSE (1 << 0)
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#define DEV_FLAGS_ANYUSE (1 << 1)
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#define DEV_FLAGS_OUT (1 << 2)
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#define DEV_FLAGS_IN (1 << 3)
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static dbdev_tab_t dbdev_tab[] = {
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#ifdef CONFIG_SOC_AU1550
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/* UARTS */
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{ DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
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{ DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
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{ DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
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{ DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
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/* EXT DMA */
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{ DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
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/* USB DEV */
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{ DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
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{ DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
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{ DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
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{ DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
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{ DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
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{ DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
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/* PSC 0 */
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{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
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{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
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/* PSC 1 */
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{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
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{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
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/* PSC 2 */
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{ DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
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{ DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
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/* PSC 3 */
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{ DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
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{ DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
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{ DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
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{ DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
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/* MAC 0 */
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{ DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
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/* MAC 1 */
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{ DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
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#endif /* CONFIG_SOC_AU1550 */
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#ifdef CONFIG_SOC_AU1200
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{ DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
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{ DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
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{ DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
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{ DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
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{ DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
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{ DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
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{ DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
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{ DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
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{ DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
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#endif // CONFIG_SOC_AU1200
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{ DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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{ DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
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};
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#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
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static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
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static dbdev_tab_t *
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find_dbdev_id (u32 id)
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{
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int i;
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dbdev_tab_t *p;
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for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
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p = &dbdev_tab[i];
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if (p->dev_id == id)
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return p;
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}
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return NULL;
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}
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/* Allocate a channel and return a non-zero descriptor if successful.
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*/
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u32
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au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
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void (*callback)(int, void *, struct pt_regs *), void *callparam)
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{
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unsigned long flags;
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u32 used, chan, rv;
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u32 dcp;
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int i;
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dbdev_tab_t *stp, *dtp;
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chan_tab_t *ctp;
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volatile au1x_dma_chan_t *cp;
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/* We do the intialization on the first channel allocation.
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* We have to wait because of the interrupt handler initialization
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* which can't be done successfully during board set up.
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*/
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if (!dbdma_initialized)
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au1xxx_dbdma_init();
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dbdma_initialized = 1;
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if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
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return 0;
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if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
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if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
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used = 0;
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rv = 0;
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/* Check to see if we can get both channels.
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*/
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spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
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if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
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(stp->dev_flags & DEV_FLAGS_ANYUSE)) {
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/* Got source */
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stp->dev_flags |= DEV_FLAGS_INUSE;
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if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
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(dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
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/* Got destination */
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dtp->dev_flags |= DEV_FLAGS_INUSE;
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}
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else {
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/* Can't get dest. Release src.
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*/
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stp->dev_flags &= ~DEV_FLAGS_INUSE;
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used++;
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}
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}
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else {
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used++;
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}
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spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
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if (!used) {
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/* Let's see if we can allocate a channel for it.
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*/
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ctp = NULL;
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chan = 0;
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spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
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for (i=0; i<NUM_DBDMA_CHANS; i++) {
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if (chan_tab_ptr[i] == NULL) {
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/* If kmalloc fails, it is caught below same
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* as a channel not available.
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*/
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ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
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chan_tab_ptr[i] = ctp;
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ctp->chan_index = chan = i;
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break;
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}
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}
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spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
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if (ctp != NULL) {
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memset(ctp, 0, sizeof(chan_tab_t));
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dcp = DDMA_CHANNEL_BASE;
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dcp += (0x0100 * chan);
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ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
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cp = (volatile au1x_dma_chan_t *)dcp;
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ctp->chan_src = stp;
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ctp->chan_dest = dtp;
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ctp->chan_callback = callback;
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ctp->chan_callparam = callparam;
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/* Initialize channel configuration.
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*/
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i = 0;
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if (stp->dev_intlevel)
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i |= DDMA_CFG_SED;
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if (stp->dev_intpolarity)
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i |= DDMA_CFG_SP;
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if (dtp->dev_intlevel)
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i |= DDMA_CFG_DED;
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if (dtp->dev_intpolarity)
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i |= DDMA_CFG_DP;
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cp->ddma_cfg = i;
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au_sync();
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/* Return a non-zero value that can be used to
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* find the channel information in subsequent
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* operations.
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*/
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rv = (u32)(&chan_tab_ptr[chan]);
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}
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else {
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/* Release devices.
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*/
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stp->dev_flags &= ~DEV_FLAGS_INUSE;
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dtp->dev_flags &= ~DEV_FLAGS_INUSE;
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}
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}
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return rv;
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}
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/* Set the device width if source or destination is a FIFO.
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* Should be 8, 16, or 32 bits.
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*/
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u32
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au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
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{
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u32 rv;
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chan_tab_t *ctp;
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dbdev_tab_t *stp, *dtp;
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ctp = *((chan_tab_t **)chanid);
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stp = ctp->chan_src;
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dtp = ctp->chan_dest;
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rv = 0;
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if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
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rv = stp->dev_devwidth;
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stp->dev_devwidth = bits;
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}
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if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
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rv = dtp->dev_devwidth;
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dtp->dev_devwidth = bits;
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}
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return rv;
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}
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/* Allocate a descriptor ring, initializing as much as possible.
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*/
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u32
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au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
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{
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int i;
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u32 desc_base, srcid, destid;
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u32 cmd0, cmd1, src1, dest1;
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u32 src0, dest0;
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chan_tab_t *ctp;
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dbdev_tab_t *stp, *dtp;
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au1x_ddma_desc_t *dp;
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/* I guess we could check this to be within the
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* range of the table......
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*/
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ctp = *((chan_tab_t **)chanid);
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stp = ctp->chan_src;
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dtp = ctp->chan_dest;
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/* The descriptors must be 32-byte aligned. There is a
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* possibility the allocation will give us such an address,
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* and if we try that first we are likely to not waste larger
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* slabs of memory.
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*/
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desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL);
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if (desc_base == 0)
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return 0;
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if (desc_base & 0x1f) {
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/* Lost....do it again, allocate extra, and round
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* the address base.
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*/
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kfree((const void *)desc_base);
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i = entries * sizeof(au1x_ddma_desc_t);
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i += (sizeof(au1x_ddma_desc_t) - 1);
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if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
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return 0;
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desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
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}
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dp = (au1x_ddma_desc_t *)desc_base;
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/* Keep track of the base descriptor.
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*/
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ctp->chan_desc_base = dp;
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/* Initialize the rings with as much information as we know.
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*/
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srcid = stp->dev_id;
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destid = dtp->dev_id;
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cmd0 = cmd1 = src1 = dest1 = 0;
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src0 = dest0 = 0;
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cmd0 |= DSCR_CMD0_SID(srcid);
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cmd0 |= DSCR_CMD0_DID(destid);
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cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
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cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT);
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switch (stp->dev_devwidth) {
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case 8:
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cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
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break;
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case 16:
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cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
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break;
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case 32:
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default:
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cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
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break;
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}
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switch (dtp->dev_devwidth) {
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case 8:
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cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
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break;
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case 16:
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cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
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break;
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case 32:
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default:
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cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
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break;
|
|
}
|
|
|
|
/* If the device is marked as an in/out FIFO, ensure it is
|
|
* set non-coherent.
|
|
*/
|
|
if (stp->dev_flags & DEV_FLAGS_IN)
|
|
cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
|
|
if (dtp->dev_flags & DEV_FLAGS_OUT)
|
|
cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
|
|
|
|
/* Set up source1. For now, assume no stride and increment.
|
|
* A channel attribute update can change this later.
|
|
*/
|
|
switch (stp->dev_tsize) {
|
|
case 1:
|
|
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
|
|
break;
|
|
case 2:
|
|
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
|
|
break;
|
|
case 4:
|
|
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
|
|
break;
|
|
case 8:
|
|
default:
|
|
src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
|
|
break;
|
|
}
|
|
|
|
/* If source input is fifo, set static address.
|
|
*/
|
|
if (stp->dev_flags & DEV_FLAGS_IN) {
|
|
src0 = stp->dev_physaddr;
|
|
src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
|
|
}
|
|
|
|
/* Set up dest1. For now, assume no stride and increment.
|
|
* A channel attribute update can change this later.
|
|
*/
|
|
switch (dtp->dev_tsize) {
|
|
case 1:
|
|
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
|
|
break;
|
|
case 2:
|
|
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
|
|
break;
|
|
case 4:
|
|
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
|
|
break;
|
|
case 8:
|
|
default:
|
|
dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
|
|
break;
|
|
}
|
|
|
|
/* If destination output is fifo, set static address.
|
|
*/
|
|
if (dtp->dev_flags & DEV_FLAGS_OUT) {
|
|
dest0 = dtp->dev_physaddr;
|
|
dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
|
|
}
|
|
|
|
for (i=0; i<entries; i++) {
|
|
dp->dscr_cmd0 = cmd0;
|
|
dp->dscr_cmd1 = cmd1;
|
|
dp->dscr_source0 = src0;
|
|
dp->dscr_source1 = src1;
|
|
dp->dscr_dest0 = dest0;
|
|
dp->dscr_dest1 = dest1;
|
|
dp->dscr_stat = 0;
|
|
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
|
|
dp++;
|
|
}
|
|
|
|
/* Make last descrptor point to the first.
|
|
*/
|
|
dp--;
|
|
dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
|
|
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
|
|
|
|
return (u32)(ctp->chan_desc_base);
|
|
}
|
|
|
|
/* Put a source buffer into the DMA ring.
|
|
* This updates the source pointer and byte count. Normally used
|
|
* for memory to fifo transfers.
|
|
*/
|
|
u32
|
|
au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
|
|
{
|
|
chan_tab_t *ctp;
|
|
au1x_ddma_desc_t *dp;
|
|
|
|
/* I guess we could check this to be within the
|
|
* range of the table......
|
|
*/
|
|
ctp = *((chan_tab_t **)chanid);
|
|
|
|
/* We should have multiple callers for a particular channel,
|
|
* an interrupt doesn't affect this pointer nor the descriptor,
|
|
* so no locking should be needed.
|
|
*/
|
|
dp = ctp->put_ptr;
|
|
|
|
/* If the descriptor is valid, we are way ahead of the DMA
|
|
* engine, so just return an error condition.
|
|
*/
|
|
if (dp->dscr_cmd0 & DSCR_CMD0_V) {
|
|
return 0;
|
|
}
|
|
|
|
/* Load up buffer address and byte count.
|
|
*/
|
|
dp->dscr_source0 = virt_to_phys(buf);
|
|
dp->dscr_cmd1 = nbytes;
|
|
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
|
|
ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
|
|
|
|
/* Get next descriptor pointer.
|
|
*/
|
|
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
|
|
|
|
/* return something not zero.
|
|
*/
|
|
return nbytes;
|
|
}
|
|
|
|
/* Put a destination buffer into the DMA ring.
|
|
* This updates the destination pointer and byte count. Normally used
|
|
* to place an empty buffer into the ring for fifo to memory transfers.
|
|
*/
|
|
u32
|
|
au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
|
|
{
|
|
chan_tab_t *ctp;
|
|
au1x_ddma_desc_t *dp;
|
|
|
|
/* I guess we could check this to be within the
|
|
* range of the table......
|
|
*/
|
|
ctp = *((chan_tab_t **)chanid);
|
|
|
|
/* We should have multiple callers for a particular channel,
|
|
* an interrupt doesn't affect this pointer nor the descriptor,
|
|
* so no locking should be needed.
|
|
*/
|
|
dp = ctp->put_ptr;
|
|
|
|
/* If the descriptor is valid, we are way ahead of the DMA
|
|
* engine, so just return an error condition.
|
|
*/
|
|
if (dp->dscr_cmd0 & DSCR_CMD0_V)
|
|
return 0;
|
|
|
|
/* Load up buffer address and byte count.
|
|
*/
|
|
dp->dscr_dest0 = virt_to_phys(buf);
|
|
dp->dscr_cmd1 = nbytes;
|
|
dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
|
|
|
|
/* Get next descriptor pointer.
|
|
*/
|
|
ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
|
|
|
|
/* return something not zero.
|
|
*/
|
|
return nbytes;
|
|
}
|
|
|
|
/* Get a destination buffer into the DMA ring.
|
|
* Normally used to get a full buffer from the ring during fifo
|
|
* to memory transfers. This does not set the valid bit, you will
|
|
* have to put another destination buffer to keep the DMA going.
|
|
*/
|
|
u32
|
|
au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
|
|
{
|
|
chan_tab_t *ctp;
|
|
au1x_ddma_desc_t *dp;
|
|
u32 rv;
|
|
|
|
/* I guess we could check this to be within the
|
|
* range of the table......
|
|
*/
|
|
ctp = *((chan_tab_t **)chanid);
|
|
|
|
/* We should have multiple callers for a particular channel,
|
|
* an interrupt doesn't affect this pointer nor the descriptor,
|
|
* so no locking should be needed.
|
|
*/
|
|
dp = ctp->get_ptr;
|
|
|
|
/* If the descriptor is valid, we are way ahead of the DMA
|
|
* engine, so just return an error condition.
|
|
*/
|
|
if (dp->dscr_cmd0 & DSCR_CMD0_V)
|
|
return 0;
|
|
|
|
/* Return buffer address and byte count.
|
|
*/
|
|
*buf = (void *)(phys_to_virt(dp->dscr_dest0));
|
|
*nbytes = dp->dscr_cmd1;
|
|
rv = dp->dscr_stat;
|
|
|
|
/* Get next descriptor pointer.
|
|
*/
|
|
ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
|
|
|
|
/* return something not zero.
|
|
*/
|
|
return rv;
|
|
}
|
|
|
|
void
|
|
au1xxx_dbdma_stop(u32 chanid)
|
|
{
|
|
chan_tab_t *ctp;
|
|
volatile au1x_dma_chan_t *cp;
|
|
int halt_timeout = 0;
|
|
|
|
ctp = *((chan_tab_t **)chanid);
|
|
|
|
cp = ctp->chan_ptr;
|
|
cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
|
|
au_sync();
|
|
while (!(cp->ddma_stat & DDMA_STAT_H)) {
|
|
udelay(1);
|
|
halt_timeout++;
|
|
if (halt_timeout > 100) {
|
|
printk("warning: DMA channel won't halt\n");
|
|
break;
|
|
}
|
|
}
|
|
/* clear current desc valid and doorbell */
|
|
cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
|
|
au_sync();
|
|
}
|
|
|
|
/* Start using the current descriptor pointer. If the dbdma encounters
|
|
* a not valid descriptor, it will stop. In this case, we can just
|
|
* continue by adding a buffer to the list and starting again.
|
|
*/
|
|
void
|
|
au1xxx_dbdma_start(u32 chanid)
|
|
{
|
|
chan_tab_t *ctp;
|
|
volatile au1x_dma_chan_t *cp;
|
|
|
|
ctp = *((chan_tab_t **)chanid);
|
|
|
|
cp = ctp->chan_ptr;
|
|
cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
|
|
cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
|
|
au_sync();
|
|
cp->ddma_dbell = 0xffffffff; /* Make it go */
|
|
au_sync();
|
|
}
|
|
|
|
void
|
|
au1xxx_dbdma_reset(u32 chanid)
|
|
{
|
|
chan_tab_t *ctp;
|
|
au1x_ddma_desc_t *dp;
|
|
|
|
au1xxx_dbdma_stop(chanid);
|
|
|
|
ctp = *((chan_tab_t **)chanid);
|
|
ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
|
|
|
|
/* Run through the descriptors and reset the valid indicator.
|
|
*/
|
|
dp = ctp->chan_desc_base;
|
|
|
|
do {
|
|
dp->dscr_cmd0 &= ~DSCR_CMD0_V;
|
|
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
|
|
} while (dp != ctp->chan_desc_base);
|
|
}
|
|
|
|
u32
|
|
au1xxx_get_dma_residue(u32 chanid)
|
|
{
|
|
chan_tab_t *ctp;
|
|
volatile au1x_dma_chan_t *cp;
|
|
u32 rv;
|
|
|
|
ctp = *((chan_tab_t **)chanid);
|
|
cp = ctp->chan_ptr;
|
|
|
|
/* This is only valid if the channel is stopped.
|
|
*/
|
|
rv = cp->ddma_bytecnt;
|
|
au_sync();
|
|
|
|
return rv;
|
|
}
|
|
|
|
void
|
|
au1xxx_dbdma_chan_free(u32 chanid)
|
|
{
|
|
chan_tab_t *ctp;
|
|
dbdev_tab_t *stp, *dtp;
|
|
|
|
ctp = *((chan_tab_t **)chanid);
|
|
stp = ctp->chan_src;
|
|
dtp = ctp->chan_dest;
|
|
|
|
au1xxx_dbdma_stop(chanid);
|
|
|
|
if (ctp->chan_desc_base != NULL)
|
|
kfree(ctp->chan_desc_base);
|
|
|
|
stp->dev_flags &= ~DEV_FLAGS_INUSE;
|
|
dtp->dev_flags &= ~DEV_FLAGS_INUSE;
|
|
chan_tab_ptr[ctp->chan_index] = NULL;
|
|
|
|
kfree(ctp);
|
|
}
|
|
|
|
static irqreturn_t
|
|
dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
|
{
|
|
u32 intstat;
|
|
u32 chan_index;
|
|
chan_tab_t *ctp;
|
|
au1x_ddma_desc_t *dp;
|
|
volatile au1x_dma_chan_t *cp;
|
|
|
|
intstat = dbdma_gptr->ddma_intstat;
|
|
au_sync();
|
|
chan_index = au_ffs(intstat) - 1;
|
|
|
|
ctp = chan_tab_ptr[chan_index];
|
|
cp = ctp->chan_ptr;
|
|
dp = ctp->cur_ptr;
|
|
|
|
/* Reset interrupt.
|
|
*/
|
|
cp->ddma_irq = 0;
|
|
au_sync();
|
|
|
|
if (ctp->chan_callback)
|
|
(ctp->chan_callback)(irq, ctp->chan_callparam, regs);
|
|
|
|
ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
|
|
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static void
|
|
au1xxx_dbdma_init(void)
|
|
{
|
|
dbdma_gptr->ddma_config = 0;
|
|
dbdma_gptr->ddma_throttle = 0;
|
|
dbdma_gptr->ddma_inten = 0xffff;
|
|
au_sync();
|
|
|
|
if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
|
|
"Au1xxx dbdma", (void *)dbdma_gptr))
|
|
printk("Can't get 1550 dbdma irq");
|
|
}
|
|
|
|
void
|
|
au1xxx_dbdma_dump(u32 chanid)
|
|
{
|
|
chan_tab_t *ctp;
|
|
au1x_ddma_desc_t *dp;
|
|
dbdev_tab_t *stp, *dtp;
|
|
volatile au1x_dma_chan_t *cp;
|
|
|
|
ctp = *((chan_tab_t **)chanid);
|
|
stp = ctp->chan_src;
|
|
dtp = ctp->chan_dest;
|
|
cp = ctp->chan_ptr;
|
|
|
|
printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
|
|
(u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
|
|
printk("desc base %x, get %x, put %x, cur %x\n",
|
|
(u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
|
|
(u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
|
|
|
|
printk("dbdma chan %x\n", (u32)cp);
|
|
printk("cfg %08x, desptr %08x, statptr %08x\n",
|
|
cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
|
|
printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
|
|
cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
|
|
|
|
|
|
/* Run through the descriptors
|
|
*/
|
|
dp = ctp->chan_desc_base;
|
|
|
|
do {
|
|
printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
|
|
(u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
|
|
printk("src0 %08x, src1 %08x, dest0 %08x\n",
|
|
dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
|
|
printk("dest1 %08x, stat %08x, nxtptr %08x\n",
|
|
dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
|
|
dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
|
|
} while (dp != ctp->chan_desc_base);
|
|
}
|
|
|
|
#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
|
|
|