6b46340a18
In d7e81c2 (clocksource: Add clocksource_register_hz/khz interface) new
interfaces were added which simplify (and optimize) the selection of the
divisor shift/mult constants. Switch over to using this new interface.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/*
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* TCC8000 system timer setup
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*
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* (C) 2009 Hans J. Koch <hjk@linutronix.de>
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*
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* Licensed under the terms of the GPL version 2.
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*
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <asm/mach/time.h>
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#include <mach/tcc8k-regs.h>
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#include <mach/irqs.h>
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#include "common.h"
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static void __iomem *timer_base;
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static cycle_t tcc_get_cycles(struct clocksource *cs)
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{
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return __raw_readl(timer_base + TC32MCNT_OFFS);
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}
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static struct clocksource clocksource_tcc = {
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.name = "tcc_tc32",
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.rating = 200,
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.read = tcc_get_cycles,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int tcc_set_next_event(unsigned long evt,
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struct clock_event_device *unused)
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{
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unsigned long reg = __raw_readl(timer_base + TC32MCNT_OFFS);
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__raw_writel(reg + evt, timer_base + TC32CMP0_OFFS);
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return 0;
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}
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static void tcc_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long tc32irq;
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
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tc32irq |= TC32IRQ_IRQEN0;
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__raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
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break;
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case CLOCK_EVT_MODE_SHUTDOWN:
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case CLOCK_EVT_MODE_UNUSED:
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tc32irq = __raw_readl(timer_base + TC32IRQ_OFFS);
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tc32irq &= ~TC32IRQ_IRQEN0;
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__raw_writel(tc32irq, timer_base + TC32IRQ_OFFS);
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break;
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case CLOCK_EVT_MODE_PERIODIC:
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case CLOCK_EVT_MODE_RESUME:
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break;
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}
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}
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static irqreturn_t tcc8k_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = dev_id;
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/* Acknowledge TC32 interrupt by reading TC32IRQ */
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__raw_readl(timer_base + TC32IRQ_OFFS);
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct clock_event_device clockevent_tcc = {
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.name = "tcc_timer1",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.set_mode = tcc_set_mode,
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.set_next_event = tcc_set_next_event,
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.rating = 200,
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};
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static struct irqaction tcc8k_timer_irq = {
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.name = "TC32_timer",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = tcc8k_timer_interrupt,
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.dev_id = &clockevent_tcc,
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};
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static int __init tcc_clockevent_init(struct clk *clock)
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{
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unsigned int c = clk_get_rate(clock);
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clocksource_register_hz(&clocksource_tcc, c);
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clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
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clockevent_tcc.shift);
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clockevent_tcc.max_delta_ns =
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clockevent_delta2ns(0xfffffffe, &clockevent_tcc);
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clockevent_tcc.min_delta_ns =
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clockevent_delta2ns(0xff, &clockevent_tcc);
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clockevent_tcc.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_tcc);
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return 0;
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}
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void __init tcc8k_timer_init(struct clk *clock, void __iomem *base, int irq)
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{
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u32 reg;
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timer_base = base;
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tcc8k_timer_irq.irq = irq;
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/* Enable clocks */
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clk_enable(clock);
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/* Initialize 32-bit timer */
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reg = __raw_readl(timer_base + TC32EN_OFFS);
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reg &= ~TC32EN_ENABLE; /* Disable timer */
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__raw_writel(reg, timer_base + TC32EN_OFFS);
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/* Free running timer, counting from 0 to 0xffffffff */
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__raw_writel(0, timer_base + TC32EN_OFFS);
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__raw_writel(0, timer_base + TC32LDV_OFFS);
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reg = __raw_readl(timer_base + TC32IRQ_OFFS);
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reg |= TC32IRQ_IRQEN0; /* irq at match with CMP0 */
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__raw_writel(reg, timer_base + TC32IRQ_OFFS);
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__raw_writel(TC32EN_ENABLE, timer_base + TC32EN_OFFS);
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tcc_clockevent_init(clock);
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setup_irq(irq, &tcc8k_timer_irq);
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}
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