78615c4ddb
Patch series "Move the ARCH_DMA_MINALIGN definition to asm/cache.h". The ARCH_KMALLOC_MINALIGN reduction series defines a generic ARCH_DMA_MINALIGN in linux/cache.h: https://lore.kernel.org/r/20230612153201.554742-2-catalin.marinas@arm.com/ Unfortunately, this causes a duplicate definition warning for microblaze, powerpc (32-bit only) and sh as these architectures define ARCH_DMA_MINALIGN in a different file than asm/cache.h. Move the macro to asm/cache.h to avoid this issue and also bring them in line with the other architectures. This patch (of 3): The powerpc architecture defines ARCH_DMA_MINALIGN in asm/page_32.h and only if CONFIG_NOT_COHERENT_CACHE is enabled (32-bit platforms only). Move this macro to asm/cache.h to allow a generic ARCH_DMA_MINALIGN definition in linux/cache.h without redefine errors/warnings. Link: https://lkml.kernel.org/r/20230613155245.1228274-1-catalin.marinas@arm.com Link: https://lkml.kernel.org/r/20230613155245.1228274-2-catalin.marinas@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202306131053.1ybvRRhO-lkp@intel.com/ Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: John Paul Adrian Glaubitz <glaubitz@physik.fu-berlin.de> Cc: Michal Simek <monstr@monstr.eu> Cc: Rich Felker <dalias@libc.org> Cc: Vlastimil Babka <vbabka@suse.cz> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_PAGE_32_H
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#define _ASM_POWERPC_PAGE_32_H
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#include <asm/cache.h>
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#if defined(CONFIG_PHYSICAL_ALIGN) && (CONFIG_PHYSICAL_START != 0)
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#if (CONFIG_PHYSICAL_START % CONFIG_PHYSICAL_ALIGN) != 0
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#error "CONFIG_PHYSICAL_START must be a multiple of CONFIG_PHYSICAL_ALIGN"
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#endif
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#endif
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#define VM_DATA_DEFAULT_FLAGS VM_DATA_DEFAULT_FLAGS32
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#if defined(CONFIG_PPC_256K_PAGES) || \
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(defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES))
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#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2 - 2) /* 1/4 of a page */
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#else
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#define PTE_SHIFT (PAGE_SHIFT - PTE_T_LOG2) /* full page */
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#endif
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#ifndef __ASSEMBLY__
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/*
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* The basic type of a PTE - 64 bits for those CPUs with > 32 bit
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* physical addressing.
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*/
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#ifdef CONFIG_PTE_64BIT
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typedef unsigned long long pte_basic_t;
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#else
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typedef unsigned long pte_basic_t;
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#endif
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#include <asm/bug.h>
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/*
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* Clear page using the dcbz instruction, which doesn't cause any
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* memory traffic (except to write out any cache lines which get
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* displaced). This only works on cacheable memory.
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*/
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static inline void clear_page(void *addr)
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{
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unsigned int i;
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WARN_ON((unsigned long)addr & (L1_CACHE_BYTES - 1));
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for (i = 0; i < PAGE_SIZE / L1_CACHE_BYTES; i++, addr += L1_CACHE_BYTES)
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dcbz(addr);
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}
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extern void copy_page(void *to, void *from);
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#include <asm-generic/getorder.h>
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#define PGD_T_LOG2 (__builtin_ffs(sizeof(pgd_t)) - 1)
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#define PTE_T_LOG2 (__builtin_ffs(sizeof(pte_t)) - 1)
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_POWERPC_PAGE_32_H */
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